LED array chip

Details LED array chip LED array chip

1999-12-27

2003-02-04

Chaudhuri, Olik (Department: 2813)

Active solid-state devices (e.g., transistors, solid-state diode

Incoherent light emitter structure

Plural light emitting devices

C438S033000, C438S068000, C438S462000

Reexamination Certificate

active

06515309

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to an LED array chip having a plurality of light-emitting elements (e.g., LEDs) and a method of manufacturing the LED array chip, and a dicing apparatus that separates a plurality of LED arrays into individual chips.
2. Description of the Related Art
FIGS. 26A-26C
illustrate the construction of a conventional LED array.
FIG. 26A
is a top view of a semiconductor wafer on which a plurality of LED arrays
100
are formed.
FIG. 26B
is a top view of one of LED arrays
100
after the semiconductor wafer has been diced.
FIG. 26C
is a cross-sectional view of the LED array
100
taken along lines D-D′ of FIG.
26
B.
FIGS. 27A and 27B
illustrate the steps of the dicing process when a conventional LED array is diced.
The LED array chip
100
includes primarily a plurality of light-emitting elements (p-type diffusion region)
5
, a plurality of individual electrodes
9
, and a common electrode
3
, all being formed on an n-type semiconductor substrate
1
. The light-emitting elements
5
are formed in a row on the surface of the n-type substrate
1
at predetermined intervals of, for example, 600 dpi or 1200 dpi. The individual electrodes
9
are formed such that a part of the electrode
9
is in contact with a part of the light-emitting element
5
. Each LED consists of the light-emitting element
5
, individual electrode
9
, n-type substrate
1
, and common electrode
3
.
The semiconductor wafer is diced using a dicing apparatus shown in
FIG. 6
, so that the plurality of LED arrays
100
are separated into individual chips.
The dicing process will be described with reference to
FIGS. 6
,
7
, and
27
.
A semiconductor wafer
20
on which a plurality of LED arrays are formed is fixedly attached to a dicing tape
24
. Then, the semiconductor wafer
20
attached on the dicing tape
24
is fixed on a stage
21
of the dicing apparatus by using a fixing jig
25
. A dicing path
101
among adjacent LED arrays
100
on the semiconductor substrate
1
is located by using a CCD camera having a magnifying lens. Then, a diamond blade
22
is positioned to cut the semiconductor wafer
20
. As shown in
FIG. 27A
, the diamond blade
22
moves across the semiconductor wafer
20
along one of two opposed lateral ends of the dicing path
101
. Then, the semiconductor wafer
20
is turned around through 180 degrees in a horizontal plane and the diamond blade
22
moves across the semiconductor wafer
20
along the other of the lateral ends of the dicing path
101
. Therefore, each LED array chip is of an inverted trapezoidal shape as shown in FIG.
26
C. LED array chips of an inverted trapezoidal shape are disclosed in, for example, Japanese Patent Preliminary Publication (KOKAI) No. 2-10879.
FIG. 28A
illustrates a rectangular cross-sectional view of another conventional LED array chip
102
.
FIG. 28B
shows an LED array chip
103
having a cross section of an inverted trapezoid.
The conventional LED arrays chips shown in
FIGS. 26C and 28A
have endmost light emitting elements close to the diced edges of the chips. Thus, chipping or cracks occur in the diced surface so that the endmost light emitting element is subject to deterioration of characteristics, e.g., leakage of light. In order to eliminate this drawback, a distance Ls between the light emitting element and the chip edge should be increased. For example, with an LED printhead, a plurality of LED array chips are arranged in a row such that the distance between endmost light emitting elements of adjacent chips must be equal to the distance between adjacent light emitting elements in each chip. Increasing the distance Ls is an obstacle to implementing high density construction of the LED printhead. Accordingly, a need exists in the art for LED array chips having shorter distance Ls.
FIG. 28B
shows still another LED array chip
103
of an inverted trapezoidal cross section with beveled surfaces
104
formed at the corners of the n-type substrate
1
. The semiconductor wafer is subjected to an etching process to form grooves in the dicing paths having walls at an obtuse angle with the chip surface. Then, the semiconductor wafer is diced as shown in
FIG. 27
, so that the LED arrays are separated into individual chips. The beveled surfaces
104
are etched surfaces and form a surface portion of the chip of a mesa shape.
For the conventional LED array chips having a mesa shape shown in
FIG. 28B
, if the LED arrays are to be of high resolution (e.g. 1200 dpi) , then the distance Ls must be still shorter. However, a shorter distance Ls again presents the problem of deteriorated characteristics such as leakage light.
The outermost dimensions of the conventional LED arrays are subjected to dicing errors (e.g., about ±4.5 &mgr;m) when the wafer is diced into individual chips using a dicing apparatus. Therefore, there are variations in the distance Ls between the endmost light emitting element and the outermost edge of the chip. Variations in the distance Ls give rise to variations in the distance between endmost LEDs of adjacent LED array chips when the LED array chips are assembled into an LED printhead.
SUMMARY OF THE INVENTION
An object of the present invention is to provide an LED chip where the light emitting elements do not deteriorate and are densely aligned.
Another object of the invention is to provide an LED chip which minimizes variations of the distance between the endmost light emitting element and the end of the chip is minimized.
An LED array chip comprises a semiconductor substrate having a front surface, a back opposing the front surface, and a side surface between the front surface and the back surface. The front surface is formed with a row of light emitting elements formed therein. The side surface has a first surface formed by etching the substrate. The first surface and the front surface come together at an end of the chip to define an end portion of the semiconductor substrate that has an acute angle between the first surface and the front surface. The end of the chip defines an outermost dimension of the chip.
The first surface extends further away from the front surface than the diffusion depth of the light emitting elements. The side surface includes a second surface that extends from the first surface to the back surface. The second surface makes substantially right angle or an obtuse angle with the back surface. The second surface is a diced surface.
A method of manufacturing an LED array chip comprising the steps of:
forming a plurality of LED arrays on a semiconductor wafer that has a front surface and a back surface opposing the front surface, the plurality of LED arrays being formed in the front surface;
forming grooves between adjacent LED arrays of the plurality of LED arrays, each of the grooves having a length extending to partition adjacent LED arrays, each of the grooves having opposing side walls each of which makes an acute angle with the front surface; and
dicing the semiconductor wafer except for the opposing side walls of each of the grooves to separate the plurality of LED arrays into individual LED array chips, the semiconductor wafer being diced such that each of the individual LED array chips has a diced surface at substantially right angle or an obtuse angle with the back surface and the diced surface extends from each of the side walls to the back surface.
The first surface of the side surface extends further away from the front surface than the diffusion depth of the light emitting elements formed in the front surface of the semiconductor wafer.
The obtuse angle is given by &thgr;b≦180°−&thgr;a, where &thgr;a is the acute angle and &thgr;b is the obtuse angle.
The grooves have a depth given by D≧2H·cot (&thgr;b−90) where D is the depth, H is a dicing error, and &thgr;b is the obtuse angle.
The method may further include the step of forming a target pattern on the back surface of the semiconductor wafer, the target pattern being positioned with respect to each of the grooves;
wherein the

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