Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-06-29
2003-02-11
Lam, Tuan T. (Department: 2816)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, 36
Reexamination Certificate
active
06519748
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a signal delay time calculation method of calculating a signal delay in a digital circuit in an LSI, and, more particularly, relates to a signal delay time calculation method of calculating a delay time in a circuit designed by using data items of actual wiring after making a layout pattern of the LSI, and relates to a computer program product for executing the signal delay time calculation method by a computer system.
2. Description of the Related Art
Recently, there is a strong progress toward miniaturization in LSI fields. In this progress, the submicron technology is thereby widely used. Therefore signal delay becomes an important element in LSI design field.
The signal delay is always divided into two parts, a cell delay and a wiring delay. The cell delay is a delay in the cell itself, which is calculated based on the state of the cell, the input signal transition time (or “transition time” in short), and a load capacity of wiring and connected pins to be driven.
The wiring delay is a delay based on a resistance in wiring, and the wiring delay is obtained by subtracting the cell delay from the entire delay.
In general, ELMORE's equation is used for calculating the wiring delay that has been disclosed in following literatures (A) and (B):
(A) “The transient response of damped linear networks with particular regard to wideband amplifiers”, W. C. Elmore, J. Appl. Physics vol.19, No.1, pp.55-63, January 1948; and
(B) “Signal Delay in RC Tree Networks”, J. Rubinstein, P. Penfield Jr., and M. A. Horowitz, IEEE Trans. on Computer-Aided Design, Vol.CAD-2, No.3, July 1983.
However, according to the trend toward the miniaturization in the LSI field where a very-small region smaller in area than a submicron region (named as “deep-submicron”) is used in order to increase the density of an LSI layout, a calculation result of the signal delay using the value “zero” as a resistance of wiring becomes not agreed with an actual delay time obtained by considering detailed wiring resistances in the LSI performed by SPICE (Simulation Program with Integrated Circuit Emphasis) and the like. In addition, the use of ELMORE's equation cannot obtain an adequate approximate-value of the delay time.
There is a phenomenon to reduce the delay time as one reason of the disagreement between these delay times, because a capacitance of a position which is separated from a driver pin through which the wiring is driven is sealed by the wiring resistance and the actual load capacitance relating to a change of the voltage of the output pin from the current voltage to the threshold voltage is smaller than that of the sum of capacitances in the load. By the presence of this phenomenon, the conventional calculation for the signal delay time outputs a larger value of a signal delay time that is greater than the actual value of the signal delay. When this calculated value of the signal delay is used, the actual circuit manufactured enters error operation even if a simulator or a static timing analyzer using the calculated delay value of the signal delay offers a guarantee that this circuit operates correctly without any error operation. An concrete example shown in
FIG. 14
, because the simulator or the static timing analyzer can use a correct delay value for the clock signal indicated by the waveform 3, and provides a larger delay value for the data bus of the waveform 1, they guarantee that the circuit has no timing error, but, actual operation causes a hold error of the waveform 2, as shown in FIG.
14
.
Although it is possible to increase the accuracy of the simulation by using a high accuracy simulator such as SPICE and to eliminate the above conventional drawback, the operation of the high accuracy simulator operates with lower speed. Accordingly, it is impossible to use the high accuracy simulator such as SPICE for a very large-scale integrated circuit because it takes a very long calculation time period. In order to avoid this problem and to calculate the delay time with higher speed, various methods other than the high accuracy simulator such as SPICE have been studied. One of them is AWE (Asymptotic Waveform Evaluation) that was proposed in about 1990. Many papers regarding AWE have been published. The following literature (C) shows a general outline of AWE in detail:
(C) “Asymptotic Waveform Evaluation for Timing Analysis”, Lawrence T. Pillage and Ronald A. Rohrer, IEEE Transaction on Computer-Aided Design, Vol.9, No.4, April 1990, 352-366.
Next, a description will be given of a brief explanation of AWE.
In AWE, a signal waveform to be finally calculated is expressed by the following equation (1)
Const
+
∑
i
n
Ki
×
exp
(
Pi
×
t
)
.
(
1
)
When Laplace transform is applied to the signal waveform (1), the following equation (2) can be obtained.
Const
s
+
∑
i
n
Ki
S
-
Pi
.
(
2
)
The equation (2) will be referred to as “waveform 1”.
Next, Laplace transform is applied to an admittance of a target circuit and a power source voltage until S
n
. By using the result, the waveform that has been obtained by performing Laplace transform for an actual signal waveform is obtained until S
n
. The result will be referred to as “waveform 2”.
In AWE, coefficients of S in both the waveform 1 and the waveform 2 are compared until n-th power, respectively, in order to obtain simultaneous equations. Then, the simultaneous equations are solved in order to obtain the values “Ki” and “Pi” in the equation (2). “Ki” is called to as “residue”, and “Pi” to as “pole”.
Section 3.3 (regarding Stability, see page p.357) in the above literature (C) described a case that there is no solution or a positive solution of the real part of the pole “Pi” in lower degree, and therefore AWE can obtain solution in a higher degree rather than the above lower degree. This means that there is no signal waveform of diverging in the calculation for a normal signal waveform and the positive solution of the real part of the pole “Pi” do not become a correct approximation in adequately large time period.
In addition, Section 3.1 (regarding AWE Approximation) in the above literature (C) described a case that a calculation value can be obtained with a third degree order time of “q” when a degree of an approximation solution is “q”. Thus, because the degree is greater, the amount of the calculation is also increased substantially. Therefore, in concrete application programs, although it is necessary to perform the calculation with a lower degree as lower as possible so that actual real parts of all poles become negative values in order to prevent the increasing of the amount of the calculation, it is difficult to determine the value of the degree correctly and efficiently.
In order to solve the above problem, namely to obtain a method of obtaining a stable solution, there was the following literatures (D) and (E):
(D) “On the Stability of Moment-Matching Approximations in Asymptotic Waveform Evaluation”, D. F. Anastasakis, N. Gopal, S. Y. Kim, and L. T. Pillage, Proceedgins 29th ACM/IEEE Design Automation Conference, 207-212; and
(E) “Method and Apparatus for Simulating a Microelectric Interconnect Circuit”, Pillage et al., U.S. Pat. No.5,379,231.
These literatures (D) and (E) disclosed the method of obtaining a pole by shifting a moment and then of obtaining a residue by using a moment that has not been shifted if it is difficult to obtain a stable solution. However, this method requires the calculation for moments as large as possible by the shift value under a prediction where a correct value can be obtained. This raises a problem to take a long calculation time.
There is a literature (F) to make a model of a cell using AWE.
(F) “A Gate-Delay Model for High-Speed CMOS Circuits”, Florentin Dartu, Noel Menezes, Jessica Qian and Lawrence T. Pillage, Proceedings 31st ACM/IEEE Design Automation Conference, 576-580.
FIGS. 15 and 16
show a model of an output pin in a cell. It is approximated that the output pin
100
in the cell
Gray Cary Ware & Freidenrich LLP
Kabushiki Kaisha Toshiba
Lam Tuan T.
Luu An T.
LandOfFree
Signal delay time calculation method of semiconductor... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Signal delay time calculation method of semiconductor..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Signal delay time calculation method of semiconductor... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3133837