Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – On insulating substrate or layer
Reexamination Certificate
1999-12-23
2003-02-25
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
On insulating substrate or layer
Reexamination Certificate
active
06524895
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a semiconductor device having a circuit constituted by thin film transistors on the substrate thereof having an insulation surface, and to a method of fabricating such a semiconductor device. More specifically, this invention relates to an electro-optical device typified by a liquid crystal display device and a construction of an electronic appliance having the electro-optical device mounted thereto.
The term “semiconductor device” used in this specification represents devices in general that function by utilizing semiconductor characteristics, and includes the electro-optical device and the electronic appliance having the electro-optical device mounted thereto, that are described above.
2. Description of the Related Art
Development of semiconductor devices having a large area integrated circuit comprising thin film transistors (hereinafter called the “TFTs”) has made a steady progress, and an active matrix liquid crystal device and an adhesion type image sensor are typical examples of such semiconductor devices.
The TFTs can be classified in accordance with their structures and their fabrication methods. The TFTs using a semiconductor film having a crystal structure as an active layer (crystalline TFTs), in particular, can form a variety of functional circuits because their field effect mobility is high.
The term “semiconductor film having the crystal structure” used in this specification represents a single crystal semiconductor, a polycrystalline semiconductor and a micro-crystal semiconductor. Furthermore, the term includes the semiconductors that are described in Japanese Patent Laid-Open Nos. Hei 7-130652(1995), Hei 8-78329(1996), Hei 10-135468(1998) and Hei 10-135469(1998).
In the active matrix liquid crystal display device, a pixel matrix circuit (also called a “pixel area”) comprising n-channel TFTs and an integrated circuit comprising a CMOS circuit as a basic circuit such as a shift register circuit, a level shifter circuit, a buffer circuit, a sampling circuit, and so forth, are formed for each functional block on one substrate.
In the adhesion type image sensor, on the other hand, integrated circuits such as a sample-and-hold circuit, a shift register circuit, a multiplexer circuit, and so forth, are formed using the TFTs.
Because the operating conditions of these circuits are not always the same, performance required for each TFT naturally varies to certain extents.
The pixel unit, for example, employs the construction that includes switching devices comprising an n-channel TFT and an auxiliary signal storage capacitance, and drives the liquid crystal by applying a voltage. The liquid crystal must be driven by an alternating current, and a system called “frame inversion driving” has been employed. Therefore, the TFTs must sufficiently reduce a leakage current as one the requisites imposed on them.
Because a high driving voltage is applied to the buffer circuit, a withstand voltage must be high. It is also necessary to sufficiently secure an ON current in order to improve current driving capacity.
However, the crystalline TFT involves the problem that its OFF current is likely to become high. From the aspect of reliability, the crystalline TFT is believed yet unequal to MOS transistors (the transistors that are fabricated on a single crystal semiconductor substrate) used for LSIs. For instance, a deterioration phenomenon such as the drop of the ON current has often been observed in the crystalline TFT. This problem results from the hot carrier effect. In other words, the hot carriers generated by a high electric field in the proximity of a drain are believed to cause this deterioration.
A lightly doped drain (LDD) structure is known as a structure of the TFT. In this structure, a low concentration impurity region is disposed between a channel region and a source or drain region into which an impurity is doped in a high concentration, and this low concentration impurity region is referred to as the “LDD” region.
The LDD structure can be further classified into a GOLD (Gate-drain Overlapped LDD) structure in which the LDD region overlaps with the gate electrode and the LDD structure in which it does not, depending on the positional relationship with the gate electrode. The GOLD structure mitigates the high electric field in the proximity of the drain, prevents the hot carrier effect and thus improves reliability. According to Mutsuko Hatano, Hajime Akimoto and Takeshi Sakai, “IEDM97 Technical Digest”, p523-526, 1997, a GOLD structure having side walls formed of silicon has been confirmed to have by far more excellent reliability than TFTs having other structures.
Nonetheless, the GOLD structure is not free from the problem that the OFF current becomes greater than the ordinary LDD structure, and it has not always been preferable to fabricate all the TFTs of a large area integrated circuit by this GOLD structure. If the OFF current increases in the n-channel TFTs constituting the pixel unit, for example, power consumption increases and abnormality is likely to appear in image display. For this reason, it is not preferable to apply as such the crystalline TFTs having the GOLD structure.
Another problem of the LDD structure is that the ON current drops with the increase of the series resistance. The ON current can be freely designed by means of the channel width of the TFT, and an offset TFT is not always necessary to be provided to the TFTs that constitute the buffer circuit, for example.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a TFT having an optimum structure by each functional circuit in a semiconductor device having a large area integrated circuit typified by an active matrix liquid crystal display device and an image sensor.
It is another object of the present invention to provide a method of fabricating such TFTs on the same substrate by the same fabrication process.
It is another object of the present invention to provide a technology for achieving the objects described above and to realize a crystalline TFT having reliability equivalent or superior to that of an MOS transistor.
It is still another object of the present invention to improve reliability of a semiconductor device having a large area integrated circuit including various functional circuits constituted by such crystalline TFTs.
In a TFT having an LDD structure, the objects described above can be accomplished by the construction in which a region where the LDD region overlaps with a gate electrode and a region where it does not are disposed in one TFT.
In order to realize TFTs having an optimum structure for each functional circuit in a semiconductor device having a large area integrated circuit typified by an active matrix liquid crystal display device and an image sensor, the present invention employs the construction in which a ratio of a region, where the LDD structure overlaps with a gate electrode, to a region where it does not is varied for each TFT.
To obtain the construction described above, the present invention employs a fabrication process that forms n-channel TFTs by a non-self-alignment process and p-channel TFTs, by a self-alignment process.
Therefore, in a semiconductor device including a semiconductor layer, a gate insulation film, a gate electrode and a gate wiring connected to the gate electrode on a substrate having an insulation surface, the present invention provides a semiconductor device having a construction wherein each of the gate electrode and the gate wiring comprises a first conductor layer, the semiconductor layer includes a channel formation region, a first impurity region of one conductivity type, a second impurity region of one conductivity type sandwiched between the channel formation region and the first impurity region of one conductivity type and keeping contact with the channel formation region, and wherein a part of the second impurity region of one conductivity type overlaps with the gate electrode through the gate insulation film.
The first c
Koyama Jun
Yamazaki Shunpei
Chaudhuri Olik
Costellia Jeffrey L.
Ha Nathan W.
Nixon & Peabody LLP
Semiconductor Energy Laboratory Co,. Ltd.
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