Semiconductor memory device with a rapid packet data input,...

Details Semiconductor memory device with a rapid packet data input,... Semiconductor memory device with a rapid packet data input,...

2001-08-30

2003-02-11

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Testing

C365S233100

Reexamination Certificate

active

06519194

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and in particular to those receiving packetized commands, addresses and the like.
2. Description of the Background Art
As microprocessors operate faster, semiconductor memory devices used as main memory therefor are also required to operate more rapidly. In recent years, to achieve more rapid operation a semiconductor memory device is changing to communicate data in synchronization with a clock signal externally applied. There is also a semiconductor memory device which takes data in at both of low to high and high to low transitions of a clock signal. Furthermore, a semiconductor memory device uses a significantly rapid clock signal to internally decode and store data and addresses transmitted in the form of a packet via address and data buses reduced in bus width.
FIG. 14
is a block diagram schematically showing a configuration of a conventional semiconductor memory device
601
receiving and transmitting commands, addresses and the like in the form of a packet.
As shown in
FIG. 14
, semiconductor memory device
601
includes a data terminal group
602
receiving data corresponding to packetized data signals DQ
0
-DQ
17
, a clock terminal pair
604
receiving complementary clock signals Ext.clkA, /Ext.clkA externally applied, a clock terminal pair
606
receiving complementary, external clock signals Ext.clkB, /Ext.clkB, an internal terminal group
603
receiving row-related commands and addresses corresponding to packetized signals RQ
5
-RQ
7
, and an input terminal group
605
receiving column-related addresses and commands corresponding to packetized signals RQ
0
-RQ
4
.
Semiconductor memory device
601
also includes a DLL circuit
610
receiving external dock signals Ext.clkA, /Ext.clkA, Ext.clkB, /Ext.clkB and outputting internal clock signals clkA and clkB, a data input/output control circuit
624
responsive in data write operation to internal clock signal clkB for receiving packetized data from data terminal group
602
and converting the packetized data to normal data and output it and responsive in data read operation to internal clock signal clkA for internally receiving normal data and converting the normal data to packetized data and outputting it to data terminal group
602
, and a DRAM core
626
operating in data write operation to store data received from data input/output control circuit
624
and operating in data read operation to output data stored therein to data input/output control circuit
624
.
Semiconductor memory device
601
also includes a serial-parallel conversion circuit
618
responsive to internal clock signal clkB for receiving packetized, row-related command, address and other signals from input terminal group
603
for serial-parallel conversion, a serial-parallel conversion circuit
620
receiving packetized, column-related address command and other signals from input terminal group
605
for serial-parallel conversion, and an interface circuit
622
responsive to internal clock it signal clkB for receiving data from serial-parallel conversion circuits
618
and
620
converted to a parallel signal, and decoding the same to apply ACT, RD, WR, PRE and other command signals timed as required to DRAM core
626
.
Semiconductor memory device
601
is synchronous with both of low to high and high to low transitions of a clock signal to externally transmit and receive data. When it receives a packetized instruction code the device internally deciphers the code and thereafter when a predetermined period of time elapses the device transmits read data or receives written data and internally writes the written data.
A semiconductor memory device receiving an address and the like in the form of a packet, as shown in
FIG. 14
, includes an interface circuit deciphering such packet data that is not mounted to conventional memories.
In a conventional semiconductor memory device, a built-in self test (BIST) is run to internally, automatically test a memory array of the device. Such an internal, automatic test, however, conventionally has not been run for testing such interface circuit.
A semiconductor memory device receiving an address and the like in the form of a packet is reduced in bus width and rapidly receives external data accordingly. As such, checking the device's operation requires a tester capable of rapid operation having an operating frequency exceeding 600 MHz. Such a high speed tester is very expensive and the cost for testing the device will thus significantly increase the cost for manufacturing the device.
SUMMARY OF THE INVENTION
The present invention contemplates a semiconductor memory device capable of operation check with a conventional tester having a low operating frequency.
Simply put, the present invention is a semiconductor memory device operating with packetized address and command signals externally received, including a test clock generation circuit, an internal packet generation circuit, a serial-parallel conversion circuit and a storage circuit.
The test clock generation circuit receives an externally applied clock signal and generates in a test mode an internal clock signal having a frequency no less than that of the clock signal. The internal packet generation circuit is responsive in the test mode to the internal clock for generating the packetized address and command signals. The serial-parallel conversion circuit in a normal mode receives the packetized address and command signals externally and in the test mode receives the packetized address and command signals from the internal packet generation circuit, the address and command signals each including a plurality of data serially input in time series, and the serial-parallel conversion circuit rearranges the plurality of data parallel to each other for output. The interface circuit receives and decodes an output from the serial-parallel conversion circuit and outputs a control signal depending on the address and command signals. The storage circuit operates to store data in response to an output from the interface circuit.
In another aspect the present invention is a semiconductor memory device including first and second internal circuits and a monitor circuit.
The second internal circuit receives an output from the first internal circuit. The monitor circuit holds an output from the first internal circuit as timed in response to an externally applied trigger signal, and externally outputs a result of holding the output from the first internal circuit thus timed.
In still another aspect the present invention is a semiconductor memory device operating with packetized address and command signals externally received, including a test clock generation circuit, a serial-parallel conversion circuit, an internal packet generation circuit, an interface circuit and a storage circuit.
The test clock generation circuit receives an externally applied clock signal and generates in a test mode an internal clock signal having a frequency no less than that of the clock signal. The serial-parallel conversion circuit in a normal mode receives the packetized address and command signals externally, the address and command signals each including a plurality of data input serially in time series, and the serial-parallel conversion circuit rearranges the plurality of data parallel to each other to provide a converted packet signal and outputting the converted packet signal. The internal packet generation circuit operates in the test mode to replace the serial-parallel conversion circuit to generate the converted packet signal in response to the internal dock. The interface circuit receives and decodes the converted packet signal and outputs a control signal depending on the address and command signals. The storage circuit operates to store data in response to an output from the interface circuit.
Advantageously, in accordance with the present invention an externally applied clock signal can be internally doubled in frequency and thus output as an internal clock sig

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