Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-01-14
2003-11-04
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S029000, C714S799000
Reexamination Certificate
active
06643803
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to digital microprocessors, and more particularly to emulating and debugging digital microprocessors.
BACKGROUND OF THE INVENTION
As the technology for manufacturing integrated circuits advances, more and more logic functions may be included in a single integrated circuit device. Modern integrated circuit (IC) devices include large numbers of gates on a single semiconductor chip, with these gates interconnected so as to perform multiple and complex functions, such as, for example, those in a general-purpose microprocessor. The manufacture of such circuits incorporating such Very Large Scale Integration (VLSI) requires that the fabrication of the circuit be error free, as some manufacturing defects may prevent it from performing all of the functions that it is designed to perform. This requires verification of the design of the circuit and also various types of electrical testing after manufacture.
In conjunction with the stuck-fault modeling and associated test generation, other circuitry may be included in the VLSI circuit specifically designed to improving its testability. One type of test circuitry is a scan path in the logic circuit. A scan path consists of a chain of synchronously clocked master/slave latches (or registers), each of which is connected to a particular node in the logic circuit. These latches can be loaded with a serial data stream (“scan in”) presetting the logic circuit nodes to a predetermined state. The logic circuit then can be exercised in normal fashion, with the result of the operation (at each of the nodes having a scan latch) stored in its respective latch. By serially unloading the contents of the latches (“scan out”), the result of the particular test operation at the associated nodes is read out and may be analyzed for improper node operation. Repetition of this operation with a number of different data patterns effectively tests all necessary combinations of the logic circuit, but with a reduced test time and cost compared to separately testing each active component or cell and all their possible interactions. Scan paths permit circuit initialization by directly writing to the latches (or registers) and directly observing the contents of the latches (or registers). Using scan paths helps to reduce the quantity of test vectors compared to traditional “functional mode” approaches. Techniques for scanning such data are discussed by E. J. McCluskey in
A Survey of Design for Testability Scan Techniques
, VLSI Design (Vol. 5, No. 12, pp. 38-61, December 1984).
Another solution is the test access port and boundary-scan architecture defined by the IEEE 1149.1 standard, a so-called JTAG test port. IEEE 1149.1 is primarily intended as a system test solution. The IEEE 1149.1 standard requires a minimum of four package pins to be dedicated to the test function. The IEEE 1149.1 standard requires boundary scan cells for each I/O buffer, which adds data delay to all normal operation function pins as well as silicon overhead. Although it has “hooks” for controlling some internal testability schemes, it is not optimized for chip-level testing. IEEE 1149.1 does not explicitly support testing of internal DC parametrics.
Software breakpoints (SWBP) provide another mechanism to allow the debug of microprocessor code and to evaluate performance. A SWBP is typically accomplished through opcode replacement, provided the program resides in a writable memory module which allows the opcode at the stop point to be replaced in memory with the software breakpoint opcode. In most machines, when a SWBP opcode reaches the first execute stage of an instruction execution pipeline, it causes the pipeline to stop advancing or trap to an interrupt service routine, and set a debug status bit indicating the pipeline has stopped or trapped. In processors classified as protected pipelines, instructions fetched into the pipeline after the SWBP are not executed. Instructions that are already in the pipeline are allowed to complete. To restart execution the pipeline can be cleared and then restarted by simply refetching the opcode at the SWBP memory address after the opcode is replaced in memory with the original opcode.
Testing and debugging such a complex pipeline is difficult, even when the techniques described in the preceding paragraphs are used. Aspects of the present invention provide improved methods and apparatus for chip-level testing, as well as system-level debugging.
SUMMARY OF THE INVENTION
Particular and preferred aspects of the invention are set out in the accompanying independent and dependent claims. Combinations of features from the dependent claims may be combined with features of the independent claims as appropriate and not merely as explicitly set out in the claims. The present invention is directed to improving the performance of processors, such as for example, but not exclusively, digital signal processors.
A digital system is provided having a processor, wherein the processor is operable to execute a sequence of instructions obtained from an instruction bus connected to an instruction memory circuit, wherein the processor comprises. The processor has system resources including registers and at least one memory circuit. The processor has test port circuitry for receiving test commands from a remote test host. Emulation circuitry for debug events is connected to the test port circuitry, operable to cause the processor to enter a debug suspend state in response to a debug event and to leave the debug suspend state to resume execution of the sequence of instruction in response to a command received by the test port circuitry, wherein execution of the sequence of instructions ceases while the processor is in the debug suspend state. The emulation circuitry is operable to access the system resources in response to an access command received by the test port circuitry. while the processor is executing the sequence of instructions such that execution of the sequence of instructions is not delayed by the access of the system resources.
According to another aspect of the present invention, the processor has an instruction pipeline operable to decode the sequence of instructions, access operands from system resources, and store results in system resources. The detection circuitry is operable to detect a bubble in the instruction pipeline during which no system resource is being accessed in response to executing the sequence of instructions. Jamming circuitry connected to the instruction pipeline is operable to jam an access for a system resource in response to the access command received by the test port circuitry into the bubble detected by the detection circuitry, whereby the access of the system resources in response to the access command is performed without delaying the instruction pipeline.
According to another aspect of the present invention, a method is provided for operating a digital system comprising a processor with system resources including registers and at least one memory circuit, comprising the steps of:
executing a sequence of instructions obtained from an instruction bus connected to an instruction memory circuit;
receiving an access command from a remote test host; and accessing the system resources in response to the access command while the processor is executing the sequence; of instructions such that execution of the sequence of instructions is not delayed by the access of the system resources.
REFERENCES:
patent: 5331571 (1994-07-01), Aronoff et al.
patent: 5737516 (1998-04-01), Circello et al.
patent: 5828824 (1998-10-01), Swoboda
patent: 5970241 (1999-10-01), Deao et al.
patent: 6032268 (2000-02-01), Swoboda et al.
patent: 6055649 (2000-04-01), Deao et al.
patent: 6065106 (2000-05-01), Deao et al.
patent: 6081885 (2000-06-01), Deao et al.
patent: 6085336 (2000-07-01), Swoboda et al.
patent: 6112298 (2000-08-01), Deao et al.
patent: 6141636 (2000-10-01), Sarno et al.
Matt David R.
Swoboda Gary L.
Baderman Scott
Bonura Tim M.
Brady III W. James
Laws Gerald E.
Telecky , Jr. Frederick J.
LandOfFree
Emulation suspend mode with instruction jamming does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Emulation suspend mode with instruction jamming, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Emulation suspend mode with instruction jamming will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3131006