Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-06-24
2003-12-30
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S316000
Reexamination Certificate
active
06670679
ABSTRACT:
BACKGROUND OF THE INVENTION
(a) Field of the Invention
The present invention relates of a semiconductor device having an ESD (electrostatic-discharge) protective circuit and, more particularly, to a semiconductor device having an ESD protective circuit for protecting the internal circuit of the semiconductor device against the ESD breakdown.
(b) Description of the Related Art
A semiconductor integrated circuit (or semiconductor device) fabricated on a semiconductor substrate generally includes semiconductor elements such as MOSFETs. It is known that MOSFETs are liable to ESD breakdown wherein an excessively high input voltage such as an electrostatic pulse voltage enters and damages the semiconductor device. Thus, a technique for protecting the semiconductor elements in the semiconductor device against the damage caused by and ESD breakdown is essential to the semiconductor device. A large number of proposals have been made and used heretofore for the technique.
Along with the higher integration of the semiconductor device as well as developments for lower operational voltage and lower power dissipation thereof, the semiconductor elements constituting the semiconductor device have more and more smaller dimensions and thereby increase in number per unit area. This leads to increase in the probability of the ESD breakdown of the semiconductor elements, especially of the MOSFETs, having smaller dimensions and packed with a higher density.
In the semiconductor device including semiconductor elements having smaller dimensions the operational voltage of the peripheral circuit is generally higher than the operational voltage of the internal circuit. For example, the peripheral circuit operates on a 5-volt power source whereas the internal circuit operates on a 2-volt power source. Accordingly, the gate insulation films of the MOSFETs have a larger thickness in the peripheral circuit than in the internal circuit.
In addition, a system-on-chip configuration having a combination of memory, logic and analog circuits is more and more employed in the semiconductor devices. Among others, the combination device having a flash memory or nonvolatile memory and a logic circuit includes a larger number of floating gate MOSFETs. The floating gate MOSFETs are not used in a semiconductor device having no non-volatile memory heretofore.
A conventional ESD protective circuit for protecting a semiconductor device is described in JP-A-63-202056. FIG
1
A shows the described ESD protective circuit and
FIG. 1B
shows a schematic sectional view thereof.
In
FIG. 1A
, an input
72
is connected to an input terminal
71
at one end, and also is connected at the other end to a gate of a MOSFET in an internal circuit not shown. An ESD protective nMOSFET
73
is connected between the input line
72
and the ground line VSS, the nMOSFET
73
having a gate maintained at the ground potential (VSS potential).
The nMOSFET
73
as described above has large dimensions in general. Although the ESD protective device includes the single nMOSFET
73
therein, the nMOSFET
73
acts as a bipolar transistor upon input of a high-voltage pulse. Thus, in
FIG. 1A
, a parasitic bipolar transistor
74
is depicted between the input line
72
and the ground line.
In
FIG. 1B
, the protective nMOSFET
73
is formed on a p-type semiconductor substrate
75
, wherein an n
+
-diffused region
76
constituting a drain and connected to the input terminal
71
is surrounded by an overlying gate electrode
77
, which is surrounded by another n
+
-diffused region
78
constituting a source.
The parasitic NPN bipolar transistor
74
depicted by dotted lines includes a base at the semiconductor substrate
75
, an emitter at the source
78
of the nMOSFET
73
and a collector at the drain
76
of the nMOSFET
73
. It is to be noted that the source
78
is connected to the ground line VSS, and the input terminal
71
implemented by a metallic pad is formed on the drain
76
.
In the conventional semiconductor device of
FIGS. 1A and 1B
, if an excessively high input voltage is applied to the drain
76
through the input lien
71
, an avalanche breakdown first occurs at the p-n junction formed just under the gate electrode
77
between the semiconductor substrate
75
and the drain
76
. The avalanche breakdown generates a large number of positive holes as majority carriers. The positive holes thus generated raises the potential of the semiconductor substrate
15
to a positive side, which allows the parasitic bipolar transistor to operate in a snapback mode. The snapback mode of the parasitic bipolar transistor turns ON the nMOSFET, which discharges and lowers the potential of the drain
76
caused by the excessively high input voltage.
The avalanche breakdown of the p-n junction is generally local in the nMOSFET having larger dimensions. In this case, the bipolar mode caused by the avalanche breakdown remains in the limited area of the nMOSFET here the breakdown first occurred. Thus, the local area at which the avalanche breakdown first occurred is likely to be damaged by the ESD breakdown. The locality of the bipolar mode of the nMOSFET is enhanced by an LDD structure of the diffused regions, whereby the local breakdown is more likely in the MOSFET having the LDD structure.
In addition, the nMOSFET is liable to damages by a breakdown in the gate insulation film thereof. The breakdown in the gate insulation film occurs more frequently in the case of a MOSFET having smaller dimensions. The breakdown in the gate insulation film is considered due to the potential rise of the semiconductor substrate caused by the avalanche breakdown generating a large number of positive holes. The positive holes entering the gate insulation film
17
from the semiconductor substrate
15
more raises the potential of the gate insulation film compared to the semiconductor substrate
15
.
FIG. 2
shows another conventional ESD protective circuit, wherein an input line
82
is connected to an input terminal
81
and also connected to a gate of MOSFET in an internal circuit not shown. The protective circuit includes a pMOSFET
83
connected between the high-voltage power source line (VCC line) and the input line
82
, and an nMOSFET
84
connected between the input line
82
and the ground line VSS. The pMOSFET
83
has a gate and a backgate (or well) both connected to the VCC line. The nMOSFET
84
has a gate and a backgate (or well) both connected to the ground line VSS.
If an excessively high input voltage having a positive polarity is applied to the input terminal
81
, positive holes are generated due to the avalanche breakdown of the p-n junction formed on the drain of the nMOSFET
84
. The positive holes raises the potential of the semiconductor substrate thereby allow the nMOSFET
84
to operate in a bipolar mode and cause a snapback breakdown. Similarly, if an excessively high voltage having a negative polarity is applied to the input terminal
81
, electrons are generated due to the avalanche breakdown of the p-n junction formed on the drain of the pMOSFET
83
. The electrons lower the potential of the semiconductor substrate, thereby allowing the pMOSFET to operate in a bipolar mode and cause a snapback breakdown. It is to be noted that the p-n junction on the drain is forward-biased if either the excessively high voltage as described above is applied to the input terminal
81
. The ESD occurs through the p-n junction constituting a diode.
In the conventional protective circuit of
FIG. 2
, if a high input voltage which does not cause the avalanche breakdown is applied to the input terminal, the protective circuit cannot respond to the high input voltage. Since the avalanche breakdown voltage cannot be adjusted to a satisfactory lower level, it is difficult to obtain a protective circuit of
FIG. 2
having a desired operational voltage. In contrast, it is possible to obtain a protective circuit of
FIG. 1A
having a desired operational voltage because a smaller gate length and a smaller thickness of the gate insulating film allow the MOSFET to re
Hayes & Soloway P.C.
Prenty Mark V.
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