Electricity: electrical systems and devices – Housing or mounting assemblies with diverse electrical... – For electronic systems and devices
Reexamination Certificate
2002-07-08
2003-06-10
Schuberg, Darren (Department: 2835)
Electricity: electrical systems and devices
Housing or mounting assemblies with diverse electrical...
For electronic systems and devices
C361S702000, C361S706000, C257S707000, C174S050510
Reexamination Certificate
active
06577503
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to semiconductor mounting packages and heat dissipation. More specifically, the present invention relates to high density vertical surface mount packages and thermal carriers for the same. This patent application is co-pending with U.S. patent application Ser. No. 09/052,446, filed Mar. 31, 1998, of Larry D. Kinsman, Jerry M. Brooks, and Walter L. Moden, entitled LOCKING ASSEMBLY FOR SECURING SEMICONDUCTOR DEVICE TO CARRIER SUBSTRATE.
2. State of the Art
Integrated circuit semiconductor devices are fabricated on wafers of silicon or gallium arsenide in such a manner as to generate many discrete output semiconductor device chips. Each of these discrete semiconductor device chips forms an integrated circuit semiconductor device die that must be packaged in order to be utilized within a computer system. One type of package encapsulates the semiconductor device die in a plastic package and bonds the die to a die mounted paddle or lead frame that then attaches to the lead frame's strips. The lead frames are then connected to pads on the semiconductor device die with the unit being encapsulated in a suitable plastic. This plastic encapsulated semiconductor device chip then undergoes a trim and form operation that separates the interconnected packages on the lead frame strips into individual entities and bends the lead package. This is the traditional and most recognized form of packaged IC chip and utilizes a highly automated manufacturing technology.
Several types of IC packages that have found favor include a package having a dual-in-line metal lead package or DIP, which typically was through-hole soldered on the printed circuit board, a pin grid array (PGA) package, which included a plurality of under lead pins that would either be through-hole soldered or inserted in a receiving unit, and a ball grid array, which uses solder balls aligned in a contact array for soldering the package onto the surface of the printed circuit board. Additionally, a new type of dual-in-line lead design has been developed and is known as the small outline J-Lead package or SOJ package. The SOJ lead package has advantages over the standard DIP design. One advantage is that the leads of an SOJ package are soldered to only one side of the circuit board, thus leaving the other side of the board free for the mounting of additional SOJ packages. Another reason is that the leads are much less vulnerable to damage prior to board assembly; hence, there are fewer rejections.
The SOJ package has extended to include a zig-zag in-line (“ZIP”) package. ZIP packages allow the package to be mounted vertically. Vertical packages have a narrower horizontal cross section than the horizontally attached DIP or SOJ or PGA packages. Because of this, vertical packages allow the distance between other vertical packages to be quite minimal compared to the horizontal packages.
In vertical packages, such as ZIP packages, all leads exit through the lower edge of the package. Since vertical packages that have a single edge must be held in place before solder reflow operation is performed when being attached to the printed circuit board, they have a limited appeal because of the difficulty in maintaining them in such a vertical position.
Solutions have been provided to position ZIP packaging vertically without the need for additional package support structure until the final attachment of the package to the circuit board during a solder reflow operation. One example of such a solution is illustrated in U.S. Pat. Reissue No. 43,794, reissued Nov. 20, 1994.
Reissue Pat. No. 43,794 is directed towards a semiconductor package having a gull-wing, zig-zag, inline-lead configuration and end-of-packaging anchoring devices. The anchoring devices allow the semiconductor package to be rigidly fixed to a circuit board such as that each lead is in compressible contact with its associated mounting pad on the board. The anchoring device includes anchoring pins having fish-hook type bars that lock against the other side of the board when the pegs are inserted through the holes. Further, the anchoring pins can be adhesively bonded in recesses provided in the circuit board. This type of arrangement has several disadvantages. One disadvantage is that the PC board or circuit board must include holes for receiving the anchoring devices. These holes may crack and cause the circuit board to split along such a fracture, thus ruining the board. Additionally, the anchoring devices are inflexible and they may fracture and break because of the bias tension placed on it against the circuit board, thus damaging the semiconductor package. Additionally, the anchoring devices must extend out from either side of the semiconductor mounting package, thus causing the anchoring devices to require additional spacing, which limits the number of packages that can be vertically mounted on the circuit board.
These vertical chip packages typically are made of plastic. Plastic, at certain thicknesses, is durable enough for the stress of the tension and flexing endured during installation and use on the PC board. Plastic, however, is a poor thermal conductor and can break easily if too much force is applied. The vertical chip packages are designed to carry complex processors that generate excess heat that must be removed. Also, multiple chip packages need good heat dissipation as well.
Accordingly, what is needed is a vertical ZIP package that has good thermal conduction as well as greater mounting strength than is otherwise possible through previous packaging designs.
BRIEF SUMMARY OF THE INVENTION
The present invention comprises high density, vertical surface mount packages and thermal carriers for the same. The semiconductor device chip package assembly includes a heat sink connected thereto.
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Brooks Jerry M.
Kinsman Larry D.
Moden Walter L.
Datskovsky Michael
Schuberg Darren
TraskBritt
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