Static information storage and retrieval – Floating gate – Particular biasing
Reexamination Certificate
2002-05-21
2003-12-09
Le, Thong (Department: 2818)
Static information storage and retrieval
Floating gate
Particular biasing
C365S189040
Reexamination Certificate
active
06661710
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This application claims priority from Korean Priority Document No. 2001-28368, filed on May 23, 2001 with the Korean Industrial Property Office, which document is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor memory devices and, more particularly, to a flash memory that is usable as a boot-up memory component in a digital information processing system such as a computer.
2. Related Art of the Invention
Nonvolatile flash memory devices such as electrically erasable and programmable read only memories (EEPROMs) are used in a variety of applications including computers, integrated circuit (IC) cards, digital cameras, camcorders, communication terminals, communication equipment, medical equipment, and automobile control systems.
NAND-type flash memories are used for mass storage because of integration advantages over NOR-type flash memories. In this regard, the NAND-type flash memories have a reduced number of pins, high bulk data transfer rate, and identical package pin configuration for high upgradeability.
In a NAND-type flash memory, a plurality of input/output (I/O) pins serve as a common port for command input, address input, and data input/output. To indicate type of information (and data) command, address to be provided is via the input/output pins. A flash memory may use several control signals or strobe signals. For example, these signals may include a chip enable signal {overscore (CE)}, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal {overscore (WE)}, a read enable signal {overscore (RE)}, a spare area enable signal {overscore (SE)}, and a read/busy signal R/{overscore (B)}.
In a personal computer system, a flash memory may be used as a system boot-up memory. During power-up, the flash memory may provide Basic Input Output System (BIOS) information which may be read from the flash memory and written into a main system memory (e.g., DRAM). During the power-up, it is necessary to provide the flash memory with control or strobe signals prior to command, address, and data inputs. This results in more complex boot-up interfacing operation than that required when using conventional mask ROMs, EPROMs, or EEPROMs.
Accordingly, a need remains for a flash memory adapted as a boot-up memory.
SUMMARY OF THE INVENTION
An object of the invention is to provide a flash memory that overcomes the disadvantages associated with prior art flash memories.
Another object of the present invention is to provide a flash memory device adapted as a boot-up memory in a digital information processing system.
Yet another object of the invention is to provide a flash memory device that has a simple bus interface.
Yet another object of the invention is to provide a flash memory device capable of reading out boot-up data during power-up without application of an external address and an external command.
Yet another object of the invention is to provide a flash memory device installed in a digital information processing system that is capable of reducing system power consumption.
Yet another object of the invention is to provide an application-specific flash memory adapted as a boot-up memory or other storage memory in a digital information processing system.
Yet another object of the invention is to provide a method of operating a flash memory device with various modes of operation.
According to an aspect of the present invention, a flash memory device is provided, which is used as a boot-up memory in a digital information processing system and is capable of reducing power consumption of the entire system as much as possible. The flash memory device can selectively be used as a boot-up memory or a normal memory for storing information except information associated with the boot-up in a digital information processing system.
The flash memory device includes a memory cell array having a plurality of nonvolatile memory cells arranged in rows and columns, and a power detecting circuit for generating a first detection signal when a power supply voltage is lower than a predetermined detection voltage. The flash memory device further includes an address generating means for internally generating an address in response to a first detection signal, a read circuit for reading data from the memory cell array in response to the internally generated address, and a control circuit for generating a control signal to selectively control activation of the read circuit in response to device information when the power supply voltage is lower than the predetermined detection voltage. The control circuit has a storage circuit for storing the device information. The device information includes information about whether or not the flash memory is used as a boot-up memory in a digital information processing system.
Only when the flash memory device is used as a boot-up memory in a system, i.e., during a boot-up period (preferably, a power-on period) of the system, the read circuit is activated in accordance with the device information such that the flash memory device can perform a boot-up data sensing operation. That is, when the flash memory device is not used as a boot-up memory, the read initiate circuit is deactivated depending on the device information during a boot-up period of the system, thereby preventing the boot-up data sensing operation of the flash memory device.
The storage circuit may be a pad formed on the flash memory device. In this case, the pad is selectively coupled to one of first and second setting voltages. Also the pad may be one of pads for interfacing the flash memory device with external devices, or one of bonding pads. One of the first and second device setting voltages is a logic zero (0) voltage, and the other is a logic one (1) voltage.
Also the storage circuit may be a fuse circuit having at least one fuse. In this case, the fuse circuit selectively supplies one of the first and second device setting voltages depending on a coupling state of the at least one fuse.
The detection voltage is an internal supply voltage. In this case, the internal supply voltage is lower than a normal power supply voltage. Alternatively, the detection voltage is lower than the power supply voltage and is higher than the internal supply voltage. Alternatively, the detection voltage may be lower than the internal supply voltage.
The address generating means preferably has an address buffer for storing an externally applied address.
As described above, only when the flash memory device is used as a boot-up memory in a system, a read circuit is activated such that the flash memory device can perform a boot-up data sensing operation thereof. On the other hand, when the flash memory device is not used as the boot-up memory, the read circuit is deactivated, and thus the flash memory device does not perform the boot-up data sense and amplify operation thereof. This prevents the flash memory device from performing unnecessary operation thereof during a boot-up period of a system, thereby reducing power consumption of the system.
In a preferred embodiment, the read circuit includes a row selecting circuit for selecting one or more rows corresponding to a row address of the internally generated address, a column selecting circuit for selecting one or more columns corresponding to a column address of the internally generated address, a page buffer for sensing data stored in memory cells of the selected columns, a read initiate circuit for generating a second detection signal when the power supply voltage reaches the predetermined detection voltage and the control signal is active, and a read controller for controlling a sensing operation of the page buffer in response to the second detection signal. When the power supply voltage is lower than the predetermined detection voltage, activation of the read initiate circuit is selectively controlled by the control signal from the control circuit. Only when the flash memory device according to this embodiment i
Le Thong
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
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