Electrical computers and digital processing systems: memory – Addressing combined with specific memory configuration or... – For multiple memory modules
Reexamination Certificate
2000-10-20
2003-10-14
Thai, Tuan V. (Department: 2186)
Electrical computers and digital processing systems: memory
Addressing combined with specific memory configuration or...
For multiple memory modules
C711S115000, C711S154000
Reexamination Certificate
active
06633948
ABSTRACT:
BACKGROUND OF THE INVENTION
In order to execute software programs, most microprocessors require at least some random access memory (RAM). The amount of RAM required by the program is dependent on the nature and complexity of the software application being processed. RAM is contained in discrete memory integrated circuits (ICs).
The RAM ICs are connected to the microprocessor through electrical connections called “nets” (also referred to as wires or traces). The amount of RAM available within a single memory IC is limited by the available manufacturing process technology. Thus, as more RAM is required, more memory ICs must be used.
Further, the microprocessor is electrically limited by the available process technology. This electrical limitation is in the maximum number of devices that can be connected to one of the microprocessor's signal pins. Specifically, each pin presents a capacitive load based on the components attached to it via an electrical net and there is a limit on the maximum capacitive load that can be driven by a signal pin. In certain cases, it is possible that the number of devices required by a microprocessor, in order to provide sufficient RAM, can exceed the number of devices that microprocessor can electrically access.
Generally, if the capacitive load is too high for the microprocessor to manage, an external device called a buffer or register is placed between the microprocessor and the memory ICs. The external buffer or register is designed to handle the higher capacitive load. Those skilled in the art will recognize that registers are distinct from buffers, and whether a buffer or register is used depends on the memory technology being used.
When an external register or buffer is used, an additional delay in the signal path is added, i.e., the maximum rate at which the memory devices can be accessed is slowed down. For higher performance, it is more desirable to use an unbuffered interface, i.e., an interface without any external buffers or registers. However, as discussed above, the combination of total memory requirement and the amount of memory available per device may require the use of a buffered or registered interface.
Also, it is often desirable to provide a microprocessor the use of both unbuffered and registered/buffered memory within the same system. However, in a situation where memory is located on a separate module attached to a microprocessor through a connector and several connectors are available for “memory expansion,” a microprocessor may not be able to access a block of unbuffered memory on another module. This results in the requirement that all modules be of the same configuration, either registered/buffered or unbuffered.
Further, when systems having small amounts of unbuffered memory are upgraded to a larger amount of memory that must be registered, e.g., because of the capacitive load created, the unbuffered memory becomes unusable to the microprocessor. As a result, the existing and still functional memory cannot be used. Thus, not only must the desired increased in capacity be purchased, but also replacements for the existing and now unusable memory must be purchased.
Referring to
FIG. 1
, in a typical computer system, a microprocessor (
10
) is connected to unbuffered RAM (
12
) and (
14
) via electrical nets (
20
). Also, or alternatively, microprocessor (
10
) is connected to registered/buffered RAM (
18
) via electrical net (
20
) which passes through register/buffer (
16
). As discussed above, those skilled in the art will appreciate that whether a register or a buffer is used is dependent on the memory technology employed.
As mentioned above, in certain situations a microprocessor is unable to access both unbuffered and registered/buffered memory in the same system. In such a case, if the system is upgraded with larger memory modules that have to be registered, registered memory must be purchased to replace all of the existing unbuffered memory modules in addition to the purchase of the upgrade memory modules.
SUMMARY OF THE INVENTION
In one aspect, a stackable dual mode memory interface comprises an interface configured to receive a first memory module, a first control circuit for switching between unbuffered and registered/buffered modes, an interface configured to receive a second memory module, and a second control circuit for switching the operation of the second memory module between unbuffered and registered/buffered modes.
In one aspect, a method of interfacing a first memory module and a second memory module with a microprocessor comprises switching between unbuffered and registered/buffered mode for the first memory module, interfacing the second memory module with the first memory module, and switching between unbuffered and registered/buffered mode for the second memory module.
In one aspect, a stackable dual mode memory interface comprises means for switching between unbuffered registered/buffered modes for a first memory module, means for interfacing a second memory module with the first memory module, and means for switching between unbuffered registered/buffered modes for the second memory module.
In one aspect, a system for using registered/buffered and unbuffered memory comprises a processor, a first memory module, an interface configured to receive a first memory module and operatively couple the first memory module to the processor, and a second memory module. The first memory module comprises a first control circuit for switching between unbuffered and registered/buffered modes, an interface configured to receive the second memory module, and a second control circuit for switching the operation of the second memory module between unbuffered and registered/buffered modes.
In one aspect, an apparatus for interfacing two memory modules comprises a processor, a first memory module, an interface configured to receive a first memory module and operatively couple the first memory module to the processor, and a second memory module. The first memory module comprises memory; connected in series with the interface configured to receive the first memory module, a first bus switch for selectively connecting the processor and the memory in an unbuffered mode; connected in parallel with the first bus switch and in series with the interface configured to receive the first memory module, a first register/buffer for selectively connecting the processor and the memory in a registered/buffered mode; and, operatively coupled to the first bus switch and the first register/buffer, enable/disable pins configured so that only one of the first bus switch and the first register/buffer is active at a time.
The first memory module also comprises an interface configured to receive the second memory module; connected in series with the interface configured to receive the second memory module, a second bus switch for selectively connecting the second memory module to the processor in an unbuffered mode; connected in parallel with the second bus switch and in series with the interface configured to receive the second memory module, a second register/buffer for selectively connecting the second memory module to the processor in a registered/buffered mode; and operatively coupled to the second bus switch and the second register/buffer, enable/disable pins configured so that only one of the second bus switch and the second register/buffer is active at a time.
Other aspects and advantages of the invention will be apparent from the following description and the appended claims.
REFERENCES:
patent: 4480307 (1984-10-01), Budde et al.
patent: 5058053 (1991-10-01), Gillett
patent: 5150279 (1992-09-01), Collins et al.
patent: 5963464 (1999-10-01), Dell et al.
patent: 6049467 (2000-04-01), Tamarkin et al.
patent: 6109929 (2000-08-01), Jasper
patent: 6425046 (2002-07-01), Leung et al.
patent: 6426560 (2002-07-01), Kawamura et al.
Hwang David S.
Pelissier Gerald R.
Rosenthal & Osha L.L.P.
Sun Microsystems Inc.
Thai Tuan V.
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