Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-07-15
2003-12-16
Flynn, Nathan J. (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S548000, C438S223000, C438S224000, C438S227000, C438S228000, C438S302000
Reexamination Certificate
active
06664602
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same.
2. Description of the Background Art
With a growing trend in recent years toward large-scale integration and miniaturization of semiconductor devices, it is becoming extremely important to reduce an isolation width between elements constituting a semiconductor device.
FIG. 28
is a sectional view showing a CMOS structure of a conventional semiconductor device. A semiconductor substrate
1
has an element isolation oxide film
3
formed in a predetermined region thereof. P wells
4
and N wells
5
are further formed in the semiconductor substrate
1
. A PMOSFET formed on an N well
5
has a P type diffusion layer
6
, and an NMOSFET formed on a P well
4
has an N type diffusion layer
7
. Illustration of gate electrodes and the like of the PMOSFET and the NMOSFET is omitted here. The element isolation oxide film
3
electrically isolates P type diffusion layers
6
formed on N wells
5
from each other, and N type diffusion layers
7
formed on P wells
4
from each other, respectively. The element isolation oxide film
3
also electrically isolates a P well
4
from a P type diffusion layer
6
formed on an N well
5
, and an N well
5
from an N type diffusion layer
7
formed on a P well
4
, respectively.
Now in reference to
FIGS. 29 through 34
, an example of steps of manufacturing the CMOS structure of the semiconductor device shown in
FIG. 28
will be described. First, an oxide film
8
is formed in a thickness of 10-30 nm on a main surface of the semiconductor substrate
1
, and a nitride film
9
is deposited thereon by 100-200 nm. Thereafter, a photoresist (not shown) is formed and patterned so that an opening is provided in a region in which the element isolation oxide film
3
is to be formed, and the photoresist is used as a mask to perform anisotropic etching, thereby forming an element isolation groove
2
having a depth of 200-400 nm in the region in which the element isolation oxide film
3
is to be formed (FIG.
29
). An oxide film to be the element isolation oxide film
3
is deposited thereon by 300-600 nm to fill in the element isolation groove
2
(FIG.
30
). Next, the element isolation oxide film
3
is planarized by means of CMP, dry etching, wet etching, or combination of these methods, while removing the element isolation oxide film
3
on the nitride film
9
(FIG.
31
). The nitride film
9
is finally removed, and the step of forming the element isolation oxide film
3
is completed (FIG.
32
).
Next, a photoresist
10
a
is formed in a thickness of 1-3 &mgr;m and patterned so that an opening is provided in a region in which a P well
4
is to be formed. Then, boron which is a P type impurity ion is implanted at an acceleration voltage of 60 keV to 180 keV and at a dose of 2×10
12
to 2×10
13
/cm
2
, thereby forming a channel cut layer
11
for preventing punch-through between elements. Thereafter, boron is further implanted at an acceleration voltage of 200 keV to 1 MeV and at a dose of 4×10
12
to 4×10
13
/cm
2
, thereby forming a retrograde well
12
(FIG.
33
). The impurity ion implantation is performed with an inclination (incident angle) of about 7 degrees for avoiding channeling. Further, doping is carried out for adjusting a threshold voltage at the NMOSFET, thereby forming the P well
4
.
Subsequently, a resist
10
b
is formed in a thickness of 1-3 &mgr;m and patterned so that an opening is provided in a region in which an N well
5
is to be formed. Then, phosphor which is an N type impurity ion is implanted at an acceleration voltage of 120 keV to 380 keV and at a dose of 2×10
12
to 2×10
13
/cm
2
, thereby forming a channel cut layer
13
for preventing punch-through between elements. Thereafter, phosphor is implanted at an acceleration voltage of 400 keV to 2 MeV and at a dose of 4×10
12
to 4×10
13
/cm
2
, thereby forming a retrograde well
14
(FIG.
34
). The implantation of phosphor is also performed with an inclination (incident angle) of about 7 degrees for avoiding channeling. Further, doping is carried out for adjusting a threshold voltage at the PMOSFET, thereby forming the N well
5
.
Although illustration is omitted, a gate electrode, a P type diffusion layers
6
and an N type diffusion layers
7
are thereafter formed, and an interlayer insulating film, a contact hole and a wiring layer are further formed, thereby completing an LSI device.
As shown in
FIG. 33
, the impurity ion implantation to form the P well
4
is performed with an inclination of about 7 degrees. In this case, due to the shadowing effect caused by the height of the resist and the presence of an impurity ion flowing in below the resist
10
a
, impurity ion distributions to be formed actually (i.e., the channel cut layer
11
and the retrograde well
12
) are shifted with respect to a position of an opening of the resist mask
10
a
. That is, the position of the P well
4
is shifted.
Further, as shown in
FIG. 34
, the impurity ion implantation to form the N well
5
is also performed with an inclination similarly to that for forming the P well
4
, so that impurity ion distributions to be formed actually (i.e., the channel cut layer
13
and the retrograde well
14
) are also shifted in the same direction as the P well
4
. That is, the position of the N well
5
is also shifted in the same direction as the P well
4
.
Therefore, according to the above-described method of manufacturing the conventional semiconductor device, the boundary between a P well
4
and an N well
5
is shifted with respect to the position of the opening of the resist mask
10
a
or
10
b
, i.e., a designed position. As a result, the distance between the N well
5
and the N type diffusion layer
7
in the P well
4
increases at a mask boundary A at the impurity ion implantation to form the wells, resulting in an increase in an isolation width (effective isolation width) which is actually effective therebetween, however, the distance between the P well
4
and the P type diffusion layer
6
in the N well
5
is reduced, which results in a reduction of an effective isolation width therebetween. On the other hand, the distance between the P well
4
and the P type diffusion layer
6
in the N well
5
increases at a mask boundary B, so that an effective isolation width therebetween increases, which, however, results in a reduction of an effective isolation width between the N well
5
and the N type diffusion layer
7
in the P well
4
. That is, the effective isolation widths between the wells and the diffusion layers become unbalanced.
FIG. 36
shows design values dn
0
and dp
0
indicating isolation widths between the N well
5
and the N type diffusion layer
7
in the P well
4
at the mask boundaries A and B, respectively. The values dn+ and dn− indicate effective isolation widths between the N well
5
and the N type diffusion layer
7
in the P well
4
at the mask boundaries A and B, respectively. The values dp− and dp+ indicate effective isolation widths between the P well
4
and the N type diffusion layer
6
in the N well
5
at the mask boundaries A and B, respectively.
FIG. 37
is a plan view for explaining the aforementioned problem of the well shift. In the drawing, P+ represents the P type diffusion layer and N+ represents the N type diffusion layer. The left direction of the drawing is defined as a 0 degree direction. For instance, when the impurity ion implantation to form the N well is performed at an incident angle of about 7 degrees from the 0 degree direction using a resist having an opening in a position for the N well indicated by solid lines as a mask, the N well is formed with a shift from the position of the opening of the resist, i.e., the designed position, as indicated by dotted lines in FIG.
37
. Further, by performing the impurity ion implantation to form the P well at an incident angle of about 7 degrees from t
Kitazawa Masashi
Yamashita Tomohiro
Mitsubishi Denki & Kabushiki Kaisha
Sefer Ahmed N.
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