Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2002-02-07
2003-08-12
Wojciechowicz, Edward (Department: 2818)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S051000, C257S316000, C257S321000, C257S322000, C257S335000, C257S336000
Reexamination Certificate
active
06605840
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates in general to a flash memory cell and its memory cell array and, more particularly, to a scalable multi-bit flash memory cell and its memory cell array.
2. Description of the Related Art
Basically, flash memory devices can be divided into two categories: a stack-gate structure and a split-gate structure. The stack-gate structure is known to be a one-transistor cell, in which the gate length of a cell can be defined by using the minimum-feature-size (F) of technology used. However, the split-gate structure including a floating-gate and a select gate is known to be a 1.5-transistor cell. Therefore, the stack-gate structure is often used in a high-density flash memory system. The stack-gate structure can be connected in series to form a high-density NAND-type array with common source/drain diffusion regions. However, the access speed is slow in an NAND-type flash memory array due to the series resistance of the configuration. Moreover, an NAND-type flash memory array is programmed by Fowler-Nordheim tunneling which is a relatively slow process. The split-gate structure having a select gate used to prevent the over-erasing problem is in general configured to form a NOR-type array and the hot-electron injection is used to obtain high-speed programming. As a consequence, a flash memory cell taking the advantages of stack-gate and split-gate structures is a major trend for development, and a typical example is shown in
FIG. 1
as disclosed by U.S. Pat. No. 5,364,806.
Referring to
FIG. 1A
, two stack-gate structures
20
G,
22
G are separated by a select gate
24
G and two common N+/N− diffusion lines
20
A,
22
A acting as the bit lines are formed in each side of the stack-gate structure. A top plan view of
FIG. 1A
is shown in
FIG. 1B
, in which a third poly-silicon layer
28
acting as a select gate is formed above the common N+/N− diffusion lines
20
A,
22
A and the control-gate lines
20
C,
22
C. From FIG.
1
A and
FIG. 1B
, four masking steps are required to implement the device and the cell size of each bit is limited to 4F
2
, which is equivalent to that of an NAND-type array using the stack-gate structure. However, there are several drawbacks as compared to existing NAND-type array: very high parasitic capacitances between the select-gate (word) line and the bit line; very high parasitic capacitances between the select-gate (word) line and the control-gate line; the isolation between the cells in the nearby word lines is poor; and the isolation between the nearby bit lines and the nearby word lines is weak. More seriously, a poor isolation between the word lines may result in an erroneous data in reading for a selected cell.
It is therefore an objective of the present invention to provide a multi-bit cell having a cell size of each bit being smaller than 4F
2
and scalable.
It is another objective of the present invention to provide a shallow-trench-isolation structure for a high-density multi-bit flash memory array.
It is further objective of the present invention to provide a better density·speed·power product for a multi-bit flash memory array.
Other objectives and advantages of the present invention will be apparent from the following description.
SUMMARY OF THE INVENTION
The scalable multi-bit flash memory cell and its memory array are disclosed by the present invention. The scalable multi-bit flash memory cell of the present invention is divided into three regions: the first-side region, the gate region, and the second-side region, in which the gate region is defined by a masking photoresist step and is therefore scalable. The gate region includes two stack-gate transistors being formed in each side portion of the gate region and one select-gate transistor being formed between two stack-gate transistors. The first-side/second-side region comprises a sidewall-oxide spacer being formed over the sidewalls of the gate region and on a portion of a flat bed and outside of a sidewall-oxide spacer comprises from top to bottom a planarized thick-oxide layer, a silicide layer, and a conductive layer formed over a portion of a flat bed. The flat bed is formed by a common-diffusion region and two etched raised field-oxide layers formed nearby and each of two stack-gate transistors comprises from top to bottom a sidewall dielectric spacer, an elongated control-gate layer formed over an intergate dielectric layer, and an integrated floating-gate layer, wherein the integrated floating-gate layer comprises a major floating-gate layer being formed over a thin tunneling-dielectric layer and two extended floating-gate layers being separately formed on a portion of each of raised field-oxide layers formed nearby. A gate-dielectric layer is formed over the planarized thick-oxide layers, two stack-gate transistors and their inner sidewalls, and a semiconductor surface between two stack-gate transistors. A planarized conductive island being patterned and etched simultaneously with a word line is formed over the gate-dielectric layer between two stack-gate transistors, wherein an implanted region is formed in the semiconductor substrate under the select-gate region with a shallow implant for threshold-voltage adjustment and a deep implant for forming a punch-through stop. The word line comprises a metal layer being formed over the gate-dielectric layer and a planarized conductive island being formed between two stack-gate transistors, and a hard masking layer including a masking dielectric layer and its two sidewall spacers being formed over the metal layer to simultaneously pattern and etch the metal layer and the planarized conductive island.
A plurality of scalable multi-bit flash memory cells of the present invention are arranged to form a scalable flash memory cell array of the present invention. A plurality of parallel shallow-trench-isolation (STI) regions are formed on a semiconductor substrate having a plurality of active regions formed therebetween, wherein each of the plurality of parallel STI regions comprises a raised field-oxide layer and each of the plurality of active regions comprises a thin tunneling dielectric layer being formed on the semiconductor substrate. A plurality of gate regions are formed over the semiconductor substrate and transversely to the plurality of parallel STI regions and a plurality of common bit-line regions are formed therebetween. Each of the plurality of gate regions includes two stack-gate regions being separately formed in each side portion and one select-gate region being formed between two stack-gate regions. Each of two stack-gate regions comprises from top to bottom a sidewall dielectric spacer, an elongated control-gate layer formed over an intergate dielectric layer, and a plurality of integrated floating-gate layers. Each of the plurality of integrated floating-gate layers comprises a major floating-gate layer being formed over a thin tunneling-dielectric layer and two extended floating-gate layers being formed separately on a portion of each of raised field-oxide layers formed nearby. Each of the plurality of common bit-line regions comprises a pair of sidewall dielectric spacers being formed over the sidewalls of the plurality of gate regions and on a portion of a flat bed, and outside of the pair of sidewall dielectric spacers further comprises a planarized thick-oxide layer, a silicide layer, and a conductive layer formed on a flat bed. The flat bed is formed alternately by common-diffusion regions and etched raised field-oxide layers. A gate-dielectric layer is formed alternately over the planarized thick-oxide layers, stack-gate regions and their inner sidewalls, and a semiconductor surface of the select-gate region, and a plurality of planarized conductive islands are formed over the gate-dielectric layer between a pair of stack-gate regions in each of the plurality of gate regions. A plurality of word lines are formed above the plurality of active regions, wherein each of the plurality of word lines comprises a metal laye
Dickinson Wright PLLC
Wojciechowicz Edward
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