Method of planarization

Details Method of planarization Method of planarization

1998-10-29

2003-08-26

Nguyen, Dung Van (Department: 3723)

Abrading

Abrading process

Utilizing fluent abradant

C451S057000, C451S059000

Reexamination Certificate

active

06609954

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of planarization. More particularly, the present invention relates to a method of forming a metallic plug within an inter-metal dielectric layer by filling metallic material into a via, and then performing a chemical-mechanical polishing (CMP) operation to remove excess metal above the plug and surrounding areas. Once the metallic layer is polished away, metallic residues above the inter-metal dielectric layer are removed by a controlled increase in the polishing rate of the dielectric layer. Consequently, undesirable metallic residues are completely removed and a planar surface is obtained at the same time.
2. Description of Related Art
Amongst the methods of planarizing a surface, chemical-mechanical polishing (CMP) is one of the most important techniques for the global planarization for VLSI or ULSI circuit fabrication. In the process of manufacturing integrated circuit devices, material often has to be removed from the surfaces of intermediate devices one or more times. Furthermore, material layers sometimes have to be planarized before carrying out the next operation. As the number of material removing operations or planarization increases, CMP operations are used more often. Chemical-mechanical polishing operates by pressing the front surface of a wafer down onto a rotating surface on a polishing table, and supplying slurry at the same time.
The slurry normally contains a chemically active component Such as an acid or a base, and a mechanically active component such as abrasive particles made from silicon dioxide. Although the physical mechanism of the polishing action is still not fully understood, the chemical reaction and the mechanical abrasion of its active components has satisfactorily polished and planarized various types of surfaces. Nowadays, CMP methods are frequently applied to the planarization of metallic and dielectric layers.
A conventional method of forming a plug includes the steps of depositing insulating material over an integrated circuit device, and then patterning the insulating layer to form a contact hole or a via opening. Finally, conductive material is deposited to fill the hole or the via so that a vertical interconnect penetrating the insulating layer and linking electrically with a portion of the device in the substrate is formed.
Since metallic conductive material such as aluminum is unable to fill the via or hole satisfactorily, a chemical vapor deposition (CVD) method is normally used to fill the via of hole with tungsten (W). In the process of depositing tungsten into the via, a layer of tungsten also forms over the insulating layer. After the via is completely filled, excess tungsten above the via needs to be removed before aluminum lines are deposited above the insulating layer and the via. An etching back method, for example, a reactive ion etching (RIE) method, can be used to remove the tungsten above the insulating layer.
However, the etching back operation can lead to over-etching, and a portion of the tungsten within the via may be removed to form a recessed cavity. Therefore, subsequently deposited aluminum layer makes poor contact with the tungsten inside the recessed cavity of the via. Furthermore. when the tungsten is etched back, microscopic particles will remain attached to the wafer surface. These attached particles can often lead to undesirable damage of the device. Hence, an alternative method of removing excessive tungsten above an insulating layer, that is, a chemical-mechanical polishing method, is often used.
FIGS. 1A through 1D
are cross-sectional views showing the progression of manufacturing steps in producing a plug according to a conventional method. Due to insufficient planarization of the inter-metal dielectric layer, recessed cavities are produced in some areas leading to device problems.
First, as shown in
FIG. 1A
, patterned conductive lines
112
are formed above a semiconductor substrate
100
. The conductive lines
112
are made of aluminum or aluminum alloy. To simplify the drawing. MOS devices and the semiconductor substrate
100
underneath the conductive lines
112
are not fully drawn. Next, a dielectric layer
114
, for example, a silicon oxide layer is deposited over the conductive layers
112
and the substrate
100
. The dielectric layer
114
is somewhat influenced by the underlying ridge pattern of the conductive lines
112
on the surface of the semiconductor substrate
100
, such that the surface of dielectric layer
114
manifests an undulated surface.
Next, as shown in
FIG. 1B
, planarization of the dielectric layer
114
is carried out. For example, a chemical-mechanical polishing method is used to form a planarized dielectric layer
114
a.
However, not all areas are planarized and some areas contain recessed cavities
116
.
Next, as shown in
FIG. 1C
, a photoresist layer (not shown in
FIG. 1C
) is formed over the dielectric layer
114
a.
The photoresist layer exposes portions of the dielectric layer
114
a
where via openings will form. Thereafter, the dielectric layer
114
a
is selectively etched using an etching technique such as a dry etching method. Ultimately, a portion of each conductive line
112
is exposed, forming via openings
126
and a dielectric layer
114
b.
In the subsequent step, a glue layer
118
conformal to the dielectric layer
114
b
is formed and covers the substrate structure Thereafter, a layer of tungsten
120
is formed over the glue layer
118
and completely fills the via openings
126
.
Next, as shown in
FIG. 1D
, a chemical-mechanical polishing operation is carried out using slurry for polishing tungsten. Hence, a portion of the tungsten layer
120
above the dielectric layer
114
b
is removed, thereby forming tungsten plugs
120
a
within the via openings
126
. However due to the presence of recessed cavities
116
on the surface of the original dielectric layer
114
b,
residual tungsten
120
b
is embedded, which makes its removal particularly difficult.
In fact, because the slurry for polishing tungsten has an especially slow removing rate for dielectric layer
114
b,
residual tungsten
120
b
entrenched inside the cavities
116
is difficult to be removed by prolonging the chemical-mechanical polishing operation. The residual tungsten
120
b
within the cavities
116
can affect the quality of a finished device, and may lead to low yield and waste of the silicon wafer.
In light of the foregoing, there is a need to improve the method of planarization.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides a planarization method that utilizes a chemical-mechanical polishing operation. Through increasing and controlling the removal rate of the inter-metal dielectric layer. recessed cavities above the dielectric layer due to an inefficient planarization technique are avoided. Therefore, device problems caused by metallic residues remaining on the dielectric surface can be reduced.
In another aspect, this invention provides a planarization method that utilizes a chemical-mechanical polishing operation. In the polishing operation, slurry especially for polishing a metallic layer is first employed to remove a greater portion of the metallic layer. Next, slurry for polishing a dielectric layer and having properties very similar to the metal-polishing slurry is added and mixed together so that polishing rate for the dielectric layer is increased. Consequently, metallic residues remaining on the dielectric layer are removed and a planar dielectric layer is obtained at the same time.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of planarization. The method includes the steps of providing a semiconductor substrate having a first metallic layer, and then forming a dielectric layer over the first metallic layer and the substrate. Next, the dielectric layer is patterned to form a via opening. Thereafter, a second metallic layer is f

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