Semiconductor memory device with boosting control circuit...

Details Semiconductor memory device with boosting control circuit... Semiconductor memory device with boosting control circuit...

2001-07-05

2003-02-25

Tran, Andrew Q. (Department: 2824)

Static information storage and retrieval

Read/write circuit

Including reference or bias voltage generator

C365S228000, C365S226000, C365S233500, C365S230060, C365S189070, C365S195000, C327S534000, C327S536000, C327S537000

Reexamination Certificate

active

06525972

ABSTRACT:

TECHNICAL FIELD
The present invention relates generally to semiconductor devices and more particularly to a semiconductor memory device having a control method that may suppress a potential reduction of a word line potential power supply upon word line selection.
BACKGROUND OF THE INVENTION
A semiconductor memory device, such as a dynamic random access memory (DRAM), can have a memory cell formed by a memory cell transistor and a memory cell capacitor. The memory cell transistor is typically an n-type insulated gate field effect transistor (IGFET). The control gate of the memory cell transistor is connected to a word line, one source/drain terminal is connected to a bit line, and another source/drain terminal is connected to the memory cell capacitor. The memory cell capacitor stores charge indicative of the logic level of the bit stored in the memory cell. Because the potential of the source of an n-type IGFET is limited to a threshold voltage (Vt) below the potential applied to the gate of the n-type IGFET, the potential held on the memory cell capacitor is limited. In the case where a power supply voltage Vint is the maximum potential applied to a word line, the memory cell capacitor has a maximum potential of Vint−Vt, where Vt is the threshold voltage of the memory cell transistor. Thus, even if a data potential corresponding to the power supply Vint is applied to the bit line, a potential of Vint−Vt is stored on the memory cell capacitor. This can effect data integrity and/or refresh specifications.
To prevent the above-mentioned problem, the word line is typically supplied with a potential higher than the power supply voltage Vint. The potential higher than the power supply voltage Vint may be considered a word line activation potential. The word line activation potential can be the potential necessary to provide adequate charge transfer to and from the memory cell capacitor.
There are two approaches for obtaining a voltage higher than the power supply voltage Vint.
One approach uses an oscillator connected to a multiplying charge pump rectifier. The approach can constantly supply a boosted voltage.
Another approach is to use a bootstrapping capacitor, such that a bootstrapping pulse can be laid over a word line supplying potential.
Referring to
FIG. 9
, a block schematic diagram of a conventional DRAM is set forth and given the general reference character
100
.
Conventional DRAM
100
includes a command decoder
101
, which decodes a command received from a central processing unit (CPU) and provides a control signal to row control circuit
104
. Also included is an address buffer
102
which receives an address signal and provides a row address to a word selection circuit
103
and a column address to a bit selection circuit
109
. Command decoder
101
provides a row enable signal RE to the address buffer
102
and word selection circuit
103
.
Conventional DRAM
100
includes an array of memory cells
110
. Memory cells (for example, memory cell
113
) are formed at the intersection of a bit line (for example, bit line
112
) and a word line (for example, word line
111
). Word selection circuit receives a boosted voltage VPP from a booster circuit
108
and based on the address value receive from address buffer
102
selects a word line
111
when the row enable signal RE becomes active. Boosted voltage VPP is applied to a selected word line
111
.
A boosted potential detection circuit
106
receives the boosted potential VPP and detects whether or not boosted potential VPP falls below a predetermined potential. Boosted potential detection circuit
106
provides a boosted voltage signal VBUP to an oscillator circuit
107
and booster circuit
108
. Oscillator circuit
107
provides an oscillation signal VBOS to the booster circuit
108
.
Sense amplifier
114
detects a data signal on a row of selected memory cells (for example, memory cells connected to selected word line
111
). Bit selection circuit
109
then selects a column (for example bit line
112
) based on a column address received from address buffer
102
. Thus, data is provided to or from the conventional DRAM
100
by way of input/output (I/O) buffer
115
.
Referring now to
FIG. 10
, a circuit schematic diagram of boosted potential detection circuit
106
is set forth. Boosted potential detection circuit
106
is the boosted potential detection circuit
106
of FIG.
9
.
Boosted potential detection circuit
106
has resistor devices (R
101
a
and R
101
b
) connected in series between boosted potential VPP and ground GND. Boosted potential VPP is connected to one terminal of resistor device R
101
a.
One terminal of resistor device R
101
b
is connected to ground GND. The other terminals of resistor devices (R
101
a
and R
101
b
) are connected to provide a potential to one input terminal of comparator circuit COM
101
. A reference potential Vs is supplied to the other input terminal of comparator circuit COM
101
. The boosted voltage signal VBUP is output from comparator COM
101
. The resistance values of resistor devices (R
101
a
and R
101
b
) are determined based on the values of the desired boosted potential VPP and reference potential Vs, so that when boosted potential is at a desired potential, a potential obtained at the connection point of resistor devices (R
101
a
and R
101
b
) is equal to the reference voltage Vs.
Referring now to
FIG. 11
, a circuit schematic diagram of oscillator circuit
107
is set forth. Oscillator circuit
107
is oscillator circuit
107
of FIG.
9
.
Oscillator circuit
107
has a NAND gate NAND
110
and inverters (IV
111
to IV
115
). NAND gate NAND
110
and inverters (IV
111
to IV
114
) are connected in series to form a ring oscillator circuit with the output of inverter IV
114
connected to an input of NAND NAND
110
. NAND gate NAND
110
also receives boosted voltage signal VBUP at an input. Inverter IV
115
is connected to receive the output of inverter IV
114
as an input and provides the oscillation signal VBOS as an output.
When boosted voltage signal VBUP is at a high logic level, oscillator circuit
107
oscillates and the oscillation signal VBOS periodically changes logic level. However, when boosted voltage signal VBUP is at a low logic level, oscillator circuit
107
stops oscillating and the oscillation signal VBOS is maintained at a predetermined logic level (logic low).
Referring now to
FIG. 13
, a schematic diagram of booster circuit
108
is set forth. Booster circuit
108
is booster circuit
108
of FIG.
9
.
Booster circuit
108
has transistors (Tr
111
and Tr
112
), inverter IV
116
, boosting capacitor Cc and smoothing capacitor Cd. Power supply voltage Vint is connected to the gate and source of transistor Tr
111
. A drain of transistor Tr
111
is connected to node a. Inverter IV
116
receives oscillation signal VBOS as an input and provides an output to a terminal of boosting capacitor Cc at node b. Another terminal of boosting capacitor Cc is connected to node a. Transistor Tr
112
has a source and gate connected to node a and a drain connected to smoothing capacitor Cd at node c. Boosted potential VPP is output at node c. Another terminal of smoothing capacitor Cd is connected to ground potential.
The operation of booster circuit
108
will now be described.
When the oscillation signal VBOS is at a logic high, node b is at a low potential. Node a is then precharged through transistor Tr
111
to a potential of power supply voltage Vint minus Vt (a threshold voltage of transistor Tr
111
). When oscillation signal VBOS transitions to a logic low, node b transitions to a high potential (Vint). Node a is then boosted to 2Vint minus Vt. Diode configured transistor Tr
112
then conducts and transfers charge from boosting capacitor Cc to smoothing capacitor Cd. Oscillation signal VBOS continues to oscillate and boosted potential VPP has a theoretical limit of (2Vint−2Vt), where 2Vt is the combined threshold voltages of transistors (Tr
111
and Tr
112
).
The boosted potential VPP can be increased by increasing the number of sta

Affiliated with

Also associated with

Rating

Semiconductor memory device with boosting control circuit... does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Semiconductor memory device with boosting control circuit..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor memory device with boosting control circuit... will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3121977