Method of forming a shallow trench isolation structure

Details Method of forming a shallow trench isolation structure Method of forming a shallow trench isolation structure

2003-02-14

2003-11-25

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Grooved and refilled with deposited dielectric material

C438S424000, C438S296000, C438S788000

Reexamination Certificate

active

06653204

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of forming a shallow trench isolation (STI) structure, and more specifically, to a method of forming a STI structure with the trench filled by a first dielectric layer formed by a-sub-atmospheric chemical vapor deposition (SACVD) process and a second dielectric layer formed by a high density plasma chemical vapor deposition (HDPCVD) process.
2. Description of the Prior Art
In semiconductor processes, in order to provide good electrical isolation, and to prevent short-circuiting between electric devices on a wafer, a localized oxidation isolation (LOCOS) process, or a shallow trench isolation (STI) process is used to insolate and protect devices. Since the field oxide layer of the LOCOS process consumes a good deal of area on the wafer, and bird's beak can occur when growing the field oxide, an STI process is typically used in the semiconductor processes when the line width is below 0.25 &mgr;m. An STI process involves first forming a shallow trench between each device, and then filling the trench with an insulating material to obtain an electrical isolation effect between each device.
Please refer to
FIG. 1
to
FIG. 3
of schematic views of forming a shallow trench isolation (STI) structure according to the prior art. As shown in
FIG. 1
, a pad oxide layer
12
is formed on a surface of a silicon substrate
10
, and a silicon nitride (SiN) layer
14
is then formed to cover the pad oxide layer
12
.
As shown in
FIG. 2
, a patterned hard mask layer
16
is then formed on the surface of the silicon substrate
10
. By performing an etching process, portions of the silicon nitride layer
14
, the pad oxide layer
12
and the substrate
10
not covered by the hard mask layer
16
are removed to form a trench
18
in portions of the silicon substrate
10
not covered by the hard mask layer
16
. As shown in
FIG. 3
, finally, the hard mask layer
16
is removed, and a high density plasma chemical vapor deposition (HDPCVD) process is performed thereafter to deposit a dielectric layer
20
, composed of silicon oxide, to fill the trench
18
and cover the silicon substrate
10
, finishing the fabrication of the STI structure according to the prior art.
As semiconductor technology progresses, manufacturing line width decreases as well, even down to less than 0.13 microns. However, as shown in
FIG. 3
, since the HDPCVD process employed in the prior art is a deposition process with low selectivity, the deposition rate of silicon oxide on exposed portions of the silicon substrate
10
within the trench
18
is similar to that on exposed portions of either the silicon nitride layer
14
or the pad oxide layer
12
within the trench
18
. Therefore, potions of the dielectric layer
20
deposited on a top surface of the silicon nitride layer
14
and on exposed portions of either the silicon nitride layer
14
or the pad oxide layer
12
within the trench
18
frequently overhang from the upper corners of the trench
18
and seal the trench
18
before the trench
18
is fully filled with the dielectric layer
20
, forming a void
22
within the trench
18
, as an aspect ratio of the trench
18
is greater than 4.0. The void
22
caused by this overhang phenomenon would lead to a defective electrical performance and a poor reliability of the device. As a result, the production yield rate of the product is seriously reduced, making the product less competitive.
SUMMARY OF THE INVENTION
It is therefore a primary object of the present invention to provide a method of forming a shallow trench isolation (STI) structure so as to prevent defective electrical performance of the device caused by a void formed in the trench.
According to the claimed invention, a pad oxide layer and a silicon nitride layer are sequentially formed on a silicon substrate. A patterned hard mask layer on a surface of the silicon substrate, and an etching process is performed to form the trench in portions of the silicon substrate not covered by the hard mask. The hard mask layer is then removed, and a sub-atmospheric chemical vapor deposition (SACVD) process is performed to selectively deposit a first dielectric layer on exposed portions of the silicon substrate within the trench. Finally, a high density plasma chemical vapor deposition (HDPCVD) process is performed to deposit a second dielectric layer on the silicon substrate.
It is an advantage of the present invention against the prior art that the present invention utilizes the SACVD process with high selectivity to deposit the first dielectric layer in the trench. Since the deposition rate of silicon oxide on exposed portions of the silicon substrate within the trench is much higher than that on exposed portions of either the silicon nitride layer or the pad oxide layer within the trench, the first dielectric layer is only deposited on exposed portions of the silicon substrate within the trench. As a result, an overhang phenomenon revealed in the prior art is prevented, and no voids would be formed in the trench to reduce electrical performance of the device, even the manufacturing line width is less than 0.13 microns and an aspect ratio of the trench is greater than 4.0. Consequently, the reliability of the product is assured, and the production yield rate is improved as well.
These and other objectives of the present invention will no doubt become obvious to those of ordinary skill in the art after reading the following detailed description of the preferred embodiment, which is illustrated in the multiple figures and drawings.


REFERENCES:
patent: 5731241 (1998-03-01), Jang et al.
patent: 5981402 (1999-11-01), Hsiao et al.
patent: 6037018 (2000-03-01), Jang et al.
patent: 6090714 (2000-07-01), Jang et al.
patent: 6191004 (2001-02-01), Hsiao
patent: 6391737 (2002-05-01), Ku et al.
patent: 6429136 (2002-08-01), Miwa

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