Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-07-13
2003-06-24
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S672000, C438S692000
Reexamination Certificate
active
06583046
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for preventing poisoning of photoresist materials during patterning of low dielectric constant (“low-k”) materials which contain at least one constituent which can cause photoresist poisoning, such as nitrogen, or where the patterning process utilizes a nitrogen-based etching/ashing chemistry. The invention has particular applicability in the manufacture of high integration density, multi-metallization level semiconductor devices comprising accurately formed, sub-micron dimensioned features and interconnection patterns while exhibiting high circuit speeds due to reduced capacitance loading.
BACKGROUND OF THE INVENTION
The escalating requirements for high integration density and performance associated with ultra-large scale (“ULSI”) integration semiconductor device wiring and interconnection patterns are difficult to satisfy in terms of providing accurately dimensioned, sub-micron sized features (e.g., 0.18 &mgr;m and below, such as 0.15 &mgr;m and below). Moreover, interconnection technology is being constantly challenged to satisfy the ever-increasing requirements for high performance (e.g., circuit speed) associated with such ULSI devices. The circuit speed of such integrated circuit (“IC”) devices varies inversely with the product of the resistance and capacitance of the interconnection system, i.e., the “RC product”. Thus, the higher the value of the RC product, the more limiting the circuit speed, and, as IC devices become more complex, with smaller feature sizes and spacings, the circuit speed becomes less dependent upon the component transistors, etc., and more dependent upon the interconnection pattern. As a consequence of the effect of the RC product upon circuit speed, at deep sub-micron regimes, e.g., less than about 0.12 &mgr;m, the performance of multi-level interconnection patterns and systems becomes dominated by the interconnect capacitance. As a further consequence, the rejection rate of IC devices due to circuit speed delays arising from RC effects has become a limiting factor in IC fabrication.
Conventional semiconductor IC devices typically comprise a semiconductor substrate, such as a doped monocrystalline silicon (Si) wafer including a plurality of active device regions, e.g., transistors, formed therein or thereon, and a plurality of overlying, sequentially formed interlayer dielectrics (“ILD”s) and electrically conductive patterns, e.g., of metal. An IC is formed therefrom containing a plurality of electrically conductive patterns comprising conductive lines separated by interwiring spaces, and a plurality of interconnect lines, such as bus lines, bit lines, word lines, and logic interconnect lines. Typically, the conductive patterns of different layers, i.e., upper and lower vertically spaced-apart layers, are electrically connected by a conductive plug filling a via opening, while a conductive plug filling a contact opening establishes an electrical contact with an active device region on or within the semiconductor substrate, such as a source or drain region of a transistor. Conductive lines are formed in trenches which typically extend substantially horizontally with respect to the semiconductor substrate. Semiconductor devices comprising five (5) or more levels of vertically interconnected metallization are becoming more prevalent as device geometries and feature sizes decrease into the deep sub-micron range.
In fabricating multi-metallization level devices such as described above, conductive plugs filling via openings for electrically interconnecting vertically spaced-apart metallization levels are typically formed by a process sequence comprising steps of: (1) depositing an inter-layer dielectric (ILD) on a patterned, electrically conductive layer, e.g., a metal layer comprising at least one metal feature; (2) forming a desired opening in the ILD, as by means of photolithographic masking and etching techniques, and filling the opening with a plug of an electrically conductive material, e.g., tungsten (W); and (3) removing excess conductive material deposited on the surface of the ILD during filling of the opening, as by chemical-mechanical polishing/planarization (“CMP”).
A commonly employed method for fabricating such electrically conductive vias for interconnecting vertically spaced-apart metallization levels is termed “damascene” processing and, in essence, involves the formation of an opening in the ILD which is filled with the plug of electrically conductive material. “Dual-damascene” processing techniques involve formation of an opening in an ILD which comprises a lower, narrower width contact or via opening section which communicates with an upper, wider trench opening section, followed by simultaneous filling of both the lower and upper sections of the opening with an electrically conductive material, typically a metal or metallic material, to simultaneously form a conductive via plug in integral communication with a conductive line.
As described above, the drive toward manufacture of ULSI semiconductor devices having decreased circuit and feature sizes well into the deep sub-micron range has necessitated a reduction in the RC product of the metallization systems. Thus, in an effort to reduce interconnect capacitance, dielectric materials having very low values of dielectric constant (permittivity) have been developed for use as ILD's in IC metallization systems formed by, e.g., the above-described damascene techniques. As compared with dielectric materials heretofore utilized as ILD's and having values of dielectric constant (“k”) in the range of from about 3.9 for dense silicon dioxide (SiO
2
) to greater than about 8 for deposited silicon nitride (Si
x
N
y
), these newer “low-k” dielectric materials are characterized by values of dielectric constant k which are less than about 3.9, e.g., about 3.5 or below (where the value of k is one (1) for a vacuum).
One type of low-k material that has been extensively studied for use as ILD's in metallization processing are flowable oxides which are, in essence, ceramic polymers, such as, for example, hydrogen silsesquioxane (“HSQ”). Such materials have been considered for use as “gap-fill” between spaced-apart metal lines in view of their flowability and ability to fill very small openings. Other possible low-k ILD materials with k values from about 2.0 to about 3.8 include FLARE 2.0™, a poly(arylene)ether (available from Advanced Microelectronic Materials Division, Allied-Signal, Sunnyvale, Calif.); Black Diamond ™ (available from Applied Materials, Santa Clara, Calif.); BCB (divinylsiloxane bis-benzocyclobutene), FO
x
,™ (HSQ-based), XLK™ (HSQ-based), and SiLK™, an aromatic hydrocarbon polymer (each available from Dow Chemical Co., Midland, Mich.); Coral™, a carbon-doped silicon oxide (available from Novellus Systems, San Jose, Calif.); HOSP™, a hybrid siloxane-organic polymer, and Nanoglass™, a nanoporous silica (each available from Honeywell Electronic Materials); and halogen-doped (e.g., fluorine-doped) silicon dioxide derived from tetraethyl orthosilicate (TEOS) and fluorine-doped silicate glass (FSG).
A drawback associated with the use of the above-described damascene technology for forming sub-micron dimensioned in-laid metallization patterns and features, particularly in the case of “via first-trench last” type dual-damascene processing, arises from a phenomenon known as “photoresist poisoning”, wherein a relatively narrow via opening is formed to extend completely through at least one ILD in a first anisotropic etching process utilizing a first patterned photoresist, and a relatively wide trench opening is formed in an upper portion of the via opening in a second anisotropic etching process utilizing a second patterned photoresist. According to such processing methodology, there is a tendency for contaminated photoresist material of the second photoresist utilized for trench opening formation to remain within the via opening in the at least one ILD after development and patterning of the second photoresist f
Gabriel Calvin T.
Okada Lynne A.
Wang Fei
Perkins Pamela E
Zarabian Amir
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