Method and arrangement for extracting capacitance in...

Details Method and arrangement for extracting capacitance in... Method and arrangement for extracting capacitance in...

2001-06-13

2003-06-17

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

Reexamination Certificate

active

06581198

ABSTRACT:

BACKGROUND OF INVENTION
An integrated circuit (“IC”) is a semiconductor device that includes many electronic components (e.g., transistors, diodes, inverters, etc.). These electrical components are interconnected to form larger scale circuit components (e.g., gates, cells, memory units, arithmetic units, controllers, decoders, etc.) on the IC. The electronic and circuit components of IC's are jointly referred to as “components.” Design engineers design IC's by transforming circuit description of the IC's into geometric descriptions, called integrated circuit layouts. To create an integrated circuit layout, design engineers typically use electronic design automation (“EDA”) application programs. These EDA application programs are computer-based tools for creating, editing, and analyzing IC design layouts. EDA applications create layouts by using geometric shapes that represent different materials and devices on integrated circuits. For instance, EDA tools commonly use rectangular lines to represent the wire segments that interconnect the IC components. These EDA tools also represent electronic and circuit IC components as geometric objects with varying shapes and sizes.
After an integrated circuit layout has been created, the integrated circuit layout is tested and optimized by EDA testing tools. Common testing and optimization steps include extraction, verification, and compaction. The steps of extraction and verification are performed to ensure that the integrated circuit layout will perform as desired.
One of the critical measurements made during the extraction process is to determine the capacitance of the various interconnect wires in the integrated circuit layout. The capacitance will help determine the performance of the integrated circuit layout. Specifically, accurate estimates of the capacitances of the complicated three-dimensional structures in an integrated circuit are important for determining final integrated circuit speeds and functionality.
The task of extracting capacitance from an integrated circuit layout is a very difficult task due to the potential interactions between a very large number of interconnect wires within close proximity to each other. New routing systems are further complicating the task of extracting capacitance from an integrated circuit layout. Thus, it is desirable to implement new methods for extracting capacitance from integrated circuit layouts.
SUMMARY OF INVENTION
The present invention introduces a method of quickly extracting the capacitance for interconnect wires in an integrated circuit routed with a non Manhattan architecture. To extract the capacitance a section containing non Manhattan wiring, the present invention proposes an approximation system that approximates the section of non Manhattan wiring with a Manhattan wiring section that has a capacitance per unit length that is linearly proportional to the length of the approximated section. The capacitance affect from the approximated Manhattan wiring section is then adjusted with a correction factor. Specifically, the present invention proposes that the capacitance be calculated for interconnect wiring sections with the following equation:
∑
i
=
1
x
⁢
Δ
⁢
 
⁢
C
i
+
l
i
×
C
i
⁢
 
Where l
i
=the length of wiring section i; and C
i
=the capacitance per unit length of the Manhattan wiring section or the approximated Manhattan wiring section i; &Dgr;C
i
=the capacitance correction factor for the approximated Manhattan wiring section i (this term is zero for Manhattan wiring sections).
Other objects, features, and advantages of present invention will be apparent from the company drawings and from the following detailed description.


REFERENCES:
patent: 5901063 (1999-05-01), Chang et al.
patent: 6209123 (2001-03-01), Maziasz et al.

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