Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-12-15
2003-11-18
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S649000, C438S655000, C438S683000
Reexamination Certificate
active
06649520
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device which reduces ohmic contact between a metal line and a substrate.
2. Background of the Related Art
A related art method for manufacturing a semiconductor device will be described with reference to
FIGS. 1
a
to
1
e.
As shown in
FIG. 1
a
, a chemical vapor deposition (CVD) oxide film
12
is formed on a semiconductor substrate
11
. A photoresist
13
is deposited on the CVD oxide film
12
and then patterned by exposure and developing processes to define a contact region.
Subsequently, the CVD oxide film
12
is selectively removed to partially expose a surface of the semiconductor substrate
11
using the patterned photoresist
13
as a mask, so that a contact hole
14
is formed.
As shown in
FIG. 1
b
, the photoresist
13
is removed and then a titanium (Ti) film
15
and a titanium nitride (TiN) film
16
are sequentially formed on an entire surface of the semiconductor substrate
11
including the contact hole
14
.
The Ti film
15
is reacted with the semiconductor substrate
11
to form a silicide, which acts as a having low resistance ohmic contact. The TiN film
16
prevents a line layer, formed later in the process, from being diffused into the substrate.
As shown in
FIG. 1
c
, an annealing process is performed in the semiconductor substrate
11
to react silicon (Si) of the semiconductor substrate
11
with Ti of the Ti film
15
, so that a silicide film
17
is formed on the interface between the semiconductor substrate
11
and the Ti film
15
.
Lit To form a film of C-
54
silicide, annealing at temperature of 850° C. or more is required. However, annealing is actually performed at about 700° C. thus forming C-
49
silicide. The resistance of C-
49
silicide film is roughly 4~5 times higher than C-
54
suicide film.
As shown in
FIG. 1
d
, a first metal layer (not shown) is formed on the entire surface of the semiconductor substrate
11
. The first metal layer is planarized by etch back process or chemical mechanical polishing (CMP) process to form a plug
18
in the contact hole
14
.
When forming the plug
18
, the CVD oxide film
12
is used as an etching end point to perform etch back process or CMP process. The Ti film
15
and the TiN film
16
over the CVD oxide film
12
are selectively removed in the etching process.
As shown in
FIG. 1
e
, a second metal layer is formed, on the plug
18
and the CVD oxide film
12
, to be electrically connected with the semiconductor substrate
11
through the plug
18
. The second metal layer is then selectively removed to form a metal line
19
.
However, the related art method for manufacturing a semiconductor device has several problems.
First, because the annealing process is performed below 850° C., the silicide film of high resistance is formed. Thus, it is difficult to minimize the resistance of the silicide layer, i.e., to produce a good ohmic contact.
Second, when compared with the Si, Ti reacts quicker with dopants such as P, As, and B causing dopant loss on the interface between the silicide film and the substrate during the annealing process. This dopant loss results in further increase in resistance, i.e., it degrades the quality of the ohmic contact. Also Ti reacts differently with As, P, and B, resulting in different electrical characteristics in N type and P type substrates.
Third, the silicide film degrades at a temperature of about 750° C. or more. It is difficult to perform annealing process into the silicide film at high temperature due to low thermal stability of the suicide film.
Fourth, since the silicide film is formed unevenly, poor contact occurs.
Finally, the TiN, used as a diffusion prevention film, is a crystal having columnar structure. Thus, it is difficult to effectively prevent the line layer from being diffused into the substrate. Particularly, TiN is not appropriate for prevention or barrier film of a line layer such as Cu, which is quickly diffused.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to devices and methods for manufacturing semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide methods for manufacturing a semiconductor device, which simply form a silicide film for reducing a resistance of an ohmic contact between a metal line and a substrate. The method also forms a ternary phase thin film to act as an amorphous diffusion prevention film between a metal line and the silicide film.
Another object of the present invention is to provide a structure for a semiconductor diffusion prevention device. The structure includes a silicide film for reducing a resistance an ohmic contact between a metal line and a substrate. The structure also includes a ternary phase film to act as a diffusion prevention film between a metal line and the silicide film.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for manufacturing a semiconductor device according to the present invention includes the steps of sequentially forming a first refractory metal and a second refractory metal on a semiconductor substrate, forming a silicide film on an interface between the semiconductor substrate and the first refractory metal, and reacting the semiconductor substrate with the first and second refractory metals on the silicide film to form a ternary phase thin film.
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patent: 5514908 (1996-05-01), Liao et al.
patent: 5545592 (1996-08-01), Iacoponi
patent: 5728625 (1998-03-01), Tung
patent: 5998873 (1999-12-01), Blair et al.
patent: 6171959 (2001-01-01), Nagabushnam
patent: 6177338 (2001-01-01), Liaw et al.
patent: 6365511 (2002-04-01), Kizilyalli et al.
patent: 408045878 (1996-02-01), None
patent: 410056176 (1998-02-01), None
Bae Jong Uk
Park Ji Soo
Sohn Dong Kyun
Birch & Stewart Kolasch & Birch, LLP
Brophy Jamie L.
Hynix / Semiconductor Inc.
Zarabian Amir
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