Non-volatile memory cell

Details Non-volatile memory cell Non-volatile memory cell

2001-08-02

2003-10-28

Smith, Matthew (Department: 2825)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S316000, C257S401000, C257S490000, C257S315000, C257S321000, C438S257000, C438S264000, C438S265000

Reexamination Certificate

active

06639270

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits, and more particularly, to an integrated circuit including a non-volatile memory cell based on a floating-gate avalanche injection metal oxide silicon (FAMOS) type transistor.
BACKGROUND OF THE INVENTION
Floating-gate avalanche injection metal oxide silicon (FAMOS) technology uses the natural memory cell obtained with a P-type MOS transistor whose single gate is insulated or electrically unconnected. This gate is therefore a floating gate.
This memory cell is called a natural memory cell because it is obtained without the addition of supplementary steps to the basic method of manufacturing a P-type MOS transistor. In particular, the memory cell has only one polysilicon level, unlike other known memory cells, for example EPROM or EEPROM type memory cells which usually have two of them. On the other hand, since the gate is electrically unconnected, it is not possible to electrically erase this memory cell. UV rays have to be used. This type of memory cell is therefore more particularly used as a one-time programmable (OTP) memory.
A diagrammatic view of a memory cell of this kind is shown in
FIG. 1
a
. In the example, the memory cell comprises a P-type MOS transistor with a gate G, a drain D and a source S. The memory cell is made in an N-type well on a P-type substrate. It therefore has a bulk connector B connected in a conventional way to the source S to eliminate the substrate effect. The only difference between the FAMOS memory cell and a usual P-type MOS transistor is that its single gate G is not electrically connected, and is therefore a floating gate.
The programming of the memory cell is obtained by hot electrons. The electrical diagram corresponding to the programming operation is shown in
FIG. 1
b
. A programming voltage VPP is applied to the source S, and ground GND is applied to the drain D. The potential of the gate G rises by capacitive coupling with the source and the bulk connection. Hot electrons are then created at the drain and injected into the gate.
In the blank state or the state in which the memory cell is erased by ultraviolet rays, a FAMOS memory cell has a threshold voltage of about −0.6 V. When programmed, this threshold voltage goes to about 1 V. Putting into effect new options of technological methods for non-volatile memories is highly costly in terms of development and testing. It is therefore especially useful to be able to integrate functions based on natural elements, directly resulting from the technology concerned and especially memory functions.
A common problem with non-volatile memories lies in their data retention. The retention of data in a FAMOS memory cell may be affected by spikes at the interface between the gate and the insulator formed around the transistor, so that the other active elements made in the substrate are insulated.
This problem is recalled with reference to
FIG. 2
, which shows a diagrammatic view of an arrangement of the PMOS transistor forming a FAMOS memory cell in a P-type substrate. Conventionally, the drain diffusion zone D and source diffusion zone S are made in an N-type well and aligned with the polysilicon gate G in the transversal direction.
Usually, the different active elements of the substrate are insulated by field oxide. The memory cell is thus insulated from the other active elements of the integrated circuit by the field oxide all round the transistor delimited by the well.
Various techniques are used to make this field oxide. These techniques include LOCOS or STI (shallow trench insulation) which gives a thinner surface oxide thickness. The interfaces
1
and
2
of this field oxide with the gate G are brittle zones of the structure due to the differences in height between the elements.
The mechanical constraints in these zones
1
,
2
may locally modify characteristics of the gate oxide of the memory cell and promote a loss of charges. For these reasons, the FAMOS memory cell does not offer a truly satisfactory data retention period.
SUMMARY OF THE INVENTION
In view of the foregoing background, it is an object of the invention to use the natural memory cell as a non-volatile memory cell in an integrated circuit.
Another object of the invention is to provide a FAMOS memory cell with improved data retention.
These and other objects, advantages and features of the invention are obtained by a ring arrangement of the memory cell, so that one of the electrodes is at the center and the other electrode is at the periphery. The gate is then inside the volume delimited by the peripheral electrode. The field oxide is outside the volume delimited by the peripheral electrode.
The invention therefore relates to a non-volatile memory cell comprising a P-type MOS transistor whose single gate is not electrically connected, and wherein this transistor has a ring arrangement. The invention also relates to an integrated circuit comprising at least one non-volatile memory cell of this type.


REFERENCES:
patent: 4942450 (1990-07-01), Iwashita
patent: 5440510 (1995-08-01), Caprara et al.
patent: 5510639 (1996-04-01), Okuda et al.
patent: 6433382 (2002-08-01), Orlowski et al.
patent: 6459121 (2002-10-01), Sakamoto et al.
patent: 0609829 (1994-08-01), None
Frohman-Bentchkowsky: “FAMOS—A New Semiconductor Charge Storage Device” Solid-State Electronics, vol. 17, No. 6, Jun. 1974, pp. 517-529, XP002165658, Elsevier Science Publishers, GB ISSN: 0038-1101.
Patent Abstracts of Japan, vol. 018, No. 556 (E-1620), Oct. 24, 1994, JP06204468A (Nippon Steel Corp.), Jul. 22, 1994.

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