Semiconductor die package including carrier with mask

Details Semiconductor die package including carrier with mask Semiconductor die package including carrier with mask

2001-04-23

2003-11-11

Coleman, William David (Department: 2823)

Semiconductor device manufacturing: process

Packaging or treatment of packaged semiconductor

Assembly of plural semiconductive substrates each possessing...

C438S109000

Reexamination Certificate

active

06645791

ABSTRACT:

BACKGROUND OF THE INVENTION
Silicon process technology has advanced significantly in the past decade. However, for the most part, decades-old package technology is often used to package semiconductor dies. In a conventional packaging process, gold wires couple a semiconductor die and a lead frame together in a semiconductor die package. Leads in the lead frame are coupled to the conductive lands on a circuit substrate such as a printed circuit board (PCB).
Advances in semiconductor processing technology, however, have made the parasitics associated with conventional packages more of a performance-limiting factor. This is particularly true in the case of power switching devices where, as in the case of power metal oxide field effect transistors (MOSFETs), the on-resistance of these devices continues to decrease. For example, the parasitic resistance introduced by the bond wires and the lead frame in conventional packages becomes much more significant for such high current devices as power MOSFETs. Furthermore, the continuous shrinking of geometries and the resulting increase in chip densities increases the demand for semiconductor packages with lead counts higher than that offered by the conventional packaging techniques.
Ball grid array and flip chip technologies were developed to address some of these demands. Both of these technologies provide for a more direct connection between the silicon die and a circuit substrate as well as providing for higher interconnect densities.
In one method for fabricating a flip chip type semiconductor die package, a vertical MOSFET device is formed in a thick semiconductor wafer (e.g., 15 to 23 mils thick) (1 mil={fraction (1/000)}
th
of an inch). A solder mask with apertures is formed on the semiconductor wafer and solder balls are deposited in the apertures. The solder balls are reflowed so that they bond to the semiconductor wafer. The semiconductor wafer is then subjected to a lapping process where the wafer is thinned to, for example, 8 mils. The semiconductor wafer is then diced to form individual semiconductor dies.
A carrier for the die package is also prepared. Solder balls are deposited on the carrier. To help balls stay in place, the solder balls are partially reflowed and subsequently bond to the carrier. A “partial” reflow process is performed at a lower temperature and/or in less time than a full reflow process. A full reflow process is not performed, since performing a full reflow process causes the solder balls to collapse and lose their shape. Once the semiconductor die and the carrier are formed, the semiconductor die can be attached to the carrier using a die attach material. The carrier and the semiconductor die can then be flipped over and then mounted to a circuit substrate such as a printed circuit board (PCB).
A number of improvements could be made to this method. For example, using two separate steps to place solder balls on the semiconductor die and the carrier increases the cost and the processing time for the package. In addition, using two steps to place solder balls on the semiconductor die and the carrier can increase the likelihood that the bumps on the two components will not be coplanar. If the ends of the solder balls on the two components are not coplanar, then all of the solder balls may not all contact the conductive lands on a circuit substrate. If this happens, interconnects between the semiconductor die and the circuit substrate may not be formed. Moreover, because the solder balls on the carrier are partially reflowed, the bonds formed between the solder balls and the carrier are weaker than if a full reflow process were performed. It would be desirable to increase the strength of the bonds formed between the solder balls and the carrier in order to improve the reliability of the formed semiconductor die package.
Embodiments of the invention address these and other problems.
SUMMARY OF THE INVENTION
One embodiment of the invention is directed to a method for forming a semiconductor die package, the method comprising: a) forming a carrier having a die attach region and an edge region, and a solder mask having one or more apertures on the edge region; b) attaching a semiconductor die to the die attach region of the carrier; and c) depositing solder in the one or more apertures in the solder mask.
Another embodiment of the invention can be directed to a method for forming a semiconductor die package, the method comprising: a) forming a carrier having a die attach region and a plurality of edge regions disposed around and at least partially defining the die attach region, wherein each edge region has a surface that is elevated with respect to the die attach region, and a first solder mask disposed on at least one of the plurality of edge regions; b) attaching a semiconductor die comprising a vertical power metal oxide field effect transistor (MOSFET) device having a source region, a drain region, and a gate region to the die attach region, and second solder mask with apertures, wherein the drain region of the semiconductor die is proximate to the die attach region and the source region is distal to the die attach region; and c) depositing solder in the apertures of the first solder mask and the apertures in the second solder mask substantially simultaneously.
Another embodiment of the invention is directed to a carrier for use in a semiconductor die package, the carrier comprising: a) a die attach region; b) an edge region; and c) a solder mask on the edge region, wherein the solder mask includes one or more apertures.
Another embodiment of the invention is directed to a semiconductor die package comprising: a) a carrier comprising a die attach region and a plurality of edge regions that are elevated with respect to and at least partially define the die attach region, and a first solder mask having one or more apertures disposed on at least one of the plurality of edge regions; b) a semiconductor die having a source region, a gate region, a drain region, and a second solder mask with one or more apertures, wherein the semiconductor die is on the die attach region and wherein the drain region is proximate to the die attach region and the source region is distal to the die attach region; and c) solder disposed within apertures in the first solder mask and the second solder mask.
These and other embodiments are described in greater detail below.


REFERENCES:
patent: 6133634 (2000-10-01), Joshi
patent: 6201305 (2001-03-01), Darveaux et al.
patent: 6284566 (2001-09-01), Lee et al.
patent: 6392290 (2002-05-01), Kasem et al.
patent: 2001/0013654 (2001-08-01), Kalidas et al.
patent: 2002/0009826 (2002-01-01), Chien

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