Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2001-04-24
2003-06-17
Thomas, Tom (Department: 2811)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000
Reexamination Certificate
active
06581195
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and apparatus for extracting information of a parasitic element which is generated in automatic placement of devices and automatic routing of wires performed in the design of a semiconductor circuit, and more particularly to a parasitic element extracting apparatus and a parasitic element extracting method in which information of a parasitic element of a semiconductor circuit is extracted from a layout of a semiconductor circuit including a wiring area of a low wire congestion on the assumption that dummy wire (hereinafter, called fill-metal) is arranged in the wiring area in which it is expected to arrange the fill-metal to smoothly perform chemical mechanical polishing.
2. Description of Related Art
As semiconductor apparatuses develop in recent years, it is desired that devices of each semiconductor apparatus are more integrated in the high density. Therefore, it is required that wiring patterns are minutely formed in manufacturing processing. In general, when devices of a semiconductor apparatus are highly integrated in the high density, a multi-layered wiring structure is formed in the semiconductor apparatus. In this multi-layered wiring structure, a plurality of wiring layers separated from each other through insulation films are arranged on a substrate of the semiconductor apparatus, and wires are arranged on each wiring layer. Each wiring layer is minutely patterned with a pattern mask in an exposure step of the manufacturing processing to precisely arrange wires on the wiring layer. Therefore, in cases where the substrate surface, on which the pattern mask is arranged, is not flat because of unevenness of the substrate surface, resolution of the patterning in the exposure step is lowered, and there is a problem that each wiring layer cannot be minutely patterned.
To avoid this problem, the substrate surface is flattened by performing chemical mechanical polishing. This chemical mechanical polishing is generally performed to remove the global unevenness of the substrate surface. In the chemical mechanical polishing, a polishing material flows into a polishing cloth arranged on the substrate surface, and the substrate surface is polished by using the polishing cloth with the polishing material. When the multi-layered wiring structure is formed in a semiconductor apparatus, a lower wiring layer is flattened according to the chemical mechanical polishing, and the exposure step is performed to produce an upper wiring layer on the lower wiring layer. Therefore, wires can be minutely formed on each wiring layer.
However, when a difference in wire congestion between wiring areas of a wiring layer is large, it is difficult to precisely flatten the surface of the wiring layer according to the chemical mechanical polishing. Therefore, to reduce the difference in the wire congestion of the wiring layer, fill-metal denoting dummy wire is inserted in the wiring area of a low wire congestion so as to make degrees of wire congestion in the wiring areas of the wiring layer agree with each other. Here, the wire congestion (or the degree of wire congestion) is defined as a value which is obtained by dividing the number of wires required in a unit lattice of a layout of a semiconductor circuit, in which wiring is roughly performed, by the number of wires which are possible to be arranged in the unit lattice of the layout of the semiconductor circuit. For example, in cases where the unit lattice denotes a square in which each side has a length equal to ten times of a wiring pitch, the number of wires possible to be arranged in the unit lattice is equal to 100. Therefore, in cases where the number of wires required for each unit lattice is equal to 100, the wire congestion is 100%.
Also, each group of integrated devices of a semiconductor circuit, which is different from individual devices, is placed in a separated area and is surrounded by an insulation film to be electrically separated from other groups of integrated devices of the semiconductor circuit, and the integrated devices of the group are connected with each other by using wires formed in a film shape to produce a circuit of the devices. In this case, parasitic elements such as wiring capacitance (or parasitic capacitance) existing between wires and parasitic inductance are parasitically formed in the separation area and the filmed wires of the integrated circuit.
Therefore, to determine the performance of the semiconductor circuit in which the automatic placement of devices and the automatic routing of wires are performed in the design processing, it is required to consider an adverse influence of the parasitic elements generated in the semiconductor circuit.
FIG. 10
is a block diagram schematically showing the configuration of a conventional parasitic element extracting apparatus in which information of a parasitic element is extracted from a layout of the semiconductor circuit in which the automatic placement of devices and the automatic routing of wires are performed. In
FIG. 10
,
100
indicates layout information of a semiconductor circuit in which the automatic placement of devices and the automatic routing of wires are performed.
101
indicates a parasitic element extracting unit for extracting information of a parasitic element from the layout information
100
of the semiconductor circuit. The operation of the parasitic element extracting unit
101
is performed by executing a program, which is prepared from data used to determine the layout of the semiconductor circuit, in a computer.
102
indicates the information of the parasitic element extracted from the layout of the semiconductor circuit by the parasitic element extracting unit
101
.
Next, an operation of the conventional parasitic element extracting apparatus is described.
When layout information
100
of the semiconductor circuit, in which the automatic placement of devices and the automatic routing of wires are performed, is received in the parasitic element extracting unit
101
, data used to determine the layout of the semiconductor circuit is extracted from the layout information
100
. Thereafter, positions of pins, routes of wires used to connect the pins with each other and positions of constituent elements (for example, layers and via holes) of the semiconductor circuit are determined according to the data, and a positional relationship of the constituent elements and sizes of the constituent elements are determined. Thereafter, in the parasitic element extracting unit
101
, information
102
of parasitic capacitance and parasitic inductance accompanying each constituent element is extracted from the layout information
100
of the semiconductor circuit according to the positional relationship of the constituent elements and the sizes of the constituent elements.
Thereafter, the information
102
of each parasitic element extracted in the parasitic element extracting unit
101
is related to the constituent element accompanied by the parasitic element for each constituent element, and the information
102
of the parasitic elements related to each constituent element is output. The information
102
of the parasitic elements is used to determine the performance of the semiconductor circuit. Also, the information
102
of the parasitic elements is used to change the design of the semiconductor circuit so as to reduce an adverse influence of the parasitic elements.
Because the conventional parasitic element extracting apparatus has the above-described configuration, the information
102
of the parasitic elements can be extracted from the layout information
100
of the semiconductor circuit in which the automatic placement of devices and the automatic routing of wires are performed. However, because influence of fill-metal inserted in the semiconductor circuit in the manufacturing processing of the semiconductor circuit is not considered, there is a problem that an expected performance of the semiconductor circuit cannot be actually obtained because o
Burns Doane , Swecker, Mathis LLP
Mitsubishi Denki & Kabushiki Kaisha
Owens Douglas W.
Thomas Tom
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