Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-03-30
2003-11-25
Nadav, Ori (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S382000, C257S384000, C257S774000
Reexamination Certificate
active
06653690
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device comprising a high density integrated circuit having a large number of insulated gate field effect transistors, and more particularly relates to a semiconductor device aiming at high density integration of transistors while reducing effects of the contact resistance against the transistor performance.
2. Description of the Related Art
Because of improvement in integration density due to the minimization of semiconductor elements, the memory capacity of dynamic random access memory (DRAM) for example, has increased by four times in three years. It is needless to say that the area of a memory cell for storing information has been reduced by minimizing the size of an element. Improvement in the aforementioned integration has been achieved, by reducing also the size of an element used for a peripheral circuit for writing and reading information stored in a memory cell.
One of the important peripheral circuits of DRAM is a sense amplifier.
FIG. 1
is a circuit diagram showing a typical sense amplifier, which is a shared sense amplifier of folded bit line structure. A sense amplifier includes a pair of bit lines BLa and BLb, which extend to memory cell array region
251
a
and
251
b
on the both sides of the sense amplifier. Respective bit lines BLa and BLb are connected with input/output lines I/Oa and I/Ob through a transistor which serves as a switch.
Also provided are transfer gate TG for selecting one of the cell array memory regions, PDL and HVCD connected with a bit line equalizer circuit, and amplifier circuit
254
. Amplifier circuit
254
, in which inputs and outputs of the two CMOS inverters consisting of N channel transistors
252
a
,
252
b
and P channel transistors
253
a
,
253
b
cross each other, is connected with bit lines BLa and BLb. A flip-flop consisting of the N channel transistor is connected with sense amplifier driving line SAN, while a flip-flop consisting of the P channel transistor is connected with sense amplifier driving line SAP.
The sense amplifier is required to have a function for detecting a small potential difference which is readout to one of the bit lines by the electric charge stored in the memory cell. The crucial point for obtaining a high performance sense amplifier is that the bit line capacity of pair of bit lines BLa and BLb, performance of elements connected with the bit lines and their resistance of wiring and contact are equal. Among others, it is important that the balance of performance of the pair of transistors constituting amplifier circuit
254
are equal to each other.
Therefore, it is desirable to make the shape and layout of component patterns constituting a pair of bit lines and elements to be connected with the bit lines equal.
FIG. 2
shows the layout pattern of typical amplifier circuit
254
. Since the sense amplifiers are arrayed in accordance with the memory cell array, patterns for the four amplifiers are shown to facilitate the explanation of the layout pattern. The amplifier circuit shown in
FIG. 2
has a structure of shared sense amplifier. The pattern width of amplifier circuit
254
is twice the pattern width of the memory cell, that is, the pitch of the bit line of amplifier circuit
254
is twice the pitch of the bit line of the memory cell.
Hereinafter, the structure of the amplifier circuit will be described in detail. As for the size of each pattern, the size of first generation
256
DRAM of minimum design dimensions 0.25 &mgr;m is given as an example. In general, the design dimensions of a peripheral circuit region is set in values larger than those of the minimum design dimensions used in the memory cell array region. The pitch of the bit line of the memory cell is 0.6 &mgr;m. The pitch of the bit line of the sense amplifier region is 1.2 &mgr;m, and the width of one amplifier circuit is 2.4 &mgr;m.
As shown in
FIG. 3
, a P well
204
is formed in N channel transistor region
201
on the surface of P-type silicon substrate
203
, and N well
205
is formed in P channel transistor region
202
. Two regions
204
and
205
are separated by field oxide film
206
formed with the ordinary selective oxidation method.
In the region where a transistor is formed except for the region of field oxide film
206
, gate oxide film
207
is formed. In the desired region on the surface of gate oxide film
207
and field oxide film
206
, formed are N gate electrode
208
and P gate electrode
209
which serve as gate electrodes of the N channel transistor and the P channel transistor, each having width 0.7 &mgr;m and consisting of an N-type polycrystalline silicon layer.
On the surface of P well
204
except for the region in which field oxide film
206
and N gate electrode
208
are formed, N-type diffusion layer
210
which serves as a source drain of the N channel transistor is formed. On the surface of N well
205
except for the region in which field oxide film
206
and P gate electrode
209
are formed, P-type diffusion layer
211
which serves as a source drain of the P channel transistor is formed.
In the desired region in inter-layer insulation film
219
, formed are N drain contact
212
having diameter of 0.4 &mgr;m and connecting N-type diffusion layer
210
which serves as a drain of the N channel transistor and bit line
216
, N gate contact
214
having diameter of 0.4 &mgr;m and connecting N gate electrode
208
and bit line
216
, P drain contact
213
having diameter of 0.4 &mgr;m and connecting P-type diffusion layer
211
which serves as a drain of the P channel transistor and bit line
216
, and P gate contact
215
having diameter of 0.4 &mgr;m and connecting P gate electrode
209
and bit line
216
.
In the above, each of N drain contact
212
, N gate contact
214
, P drain contact
213
and P gate contact
215
are formed of a contact plug embedded with barrier metal consisting of TiN/Ti and tungsten. In a desired region of inter-layer insulation film
219
, formed are N source contact
212
having diameter of 0.4 &mgr;m which is used in common in the two N channel transistors and connecting N-type diffusion layer
210
which serves as a common source of the two N channel transistors and SAN wiring
220
, and a P source contact having diameter of 0.4 &mgr;m which is used in common in the two P channel transistors and connecting P-type diffusion layer
211
which serves as a common source of the two P channel transistors and SAP wiring
221
. Each of N source contact
217
and P source contact
218
are formed of a contact plug embedded with barrier metal consisting of TiN/Ti and tungsten.
Integration of a semiconductor device has been carried out by reducing the size of elements in accordance with the scaling rule. In order to explain the effects of parasitic resistance which cause troubles when elements are reduced in size, the components constituting a transistor and resistors in the current path of the transistor are shown in FIG.
4
. According to the scaling rule, in a constant electric field where the voltage drops in proportion to a decrease in the element size, channel resistance Rch of the transistor is kept constant. On the other hand, resistance of a parasitic component such as a contact or wiring increases when the size is decreased. For example, wiring resistance (Rws, Rwd), plug resistance (Rps, Rpd) connecting the wiring and the diffusion layer and diffusion layer resistance (Rds, Rdd) increase inversely with the scaling down. Contact resistance (Rcs, Rcd) between the plug and the diffusion layer, which increases inversely with the contact area, increases in inverse square of the diameter of the contact.
When an element has larger dimensions (e.g., larger than 1 &mgr;m), since the aforementioned parasitic resistance has a sufficiently small value compared with that of the channel resistance, it has little influence over the current driving capability of the transistor. When the element is minimized to 0.5 &mgr;m or smaller, however, the parasitic resistance, the con
Foley & Lardner
Nadav Ori
NEC Electronics Corporation
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