Abrading – Flexible-member tool – per se – Interrupted or composite work face
Reexamination Certificate
2002-09-13
2003-08-05
Morgan, Eileen P. (Department: 3723)
Abrading
Flexible-member tool, per se
Interrupted or composite work face
C451S296000, C451S041000, C451S063000
Reexamination Certificate
active
06602123
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to integrated circuit fabrication and particularly to the preparation of a surface of a semiconductor wafer, commonly referred to as polarization, prior to the actual fabrication of the integrated circuits.
BACKGROUND OF THE INVENTION
Semiconductor wafers (or simply, wafers), used for the fabrication of integrated circuits, need to be made essentially flat and smooth prior to and within the process of the actual creation of the integrated circuits. The wafer must be perfectly flat and smooth in order to increase wafer yield, i.e., maximize the number of good integrated circuits created on the wafer. A wafer that is not flat or has grooves, nicks, or scratches will likely result in a significant number of faulty integrated circuits if it were to be used unpolarized to create integrated circuits.
The wafers are usually sawed from large ingots of the semiconductor material and then flattened and polished on polishing wheels and/or belts. In the process of creating integrated circuits on the wafer, several materials are deposited on the wafer, and some of these materials need to be removed. These materials may be removed in a subsequent process step, such as polishing.
Depending on the materials and/or the process requirements, the wafers are first flattened by a first polishing wheel (or belt) with a relatively coarse abrasive surface and then polished by a second polishing wheel (or belt) with a relatively fine abrasive surface. The wafer may undergo several flattening and polishing steps, depending on how flat and smooth the wafer needs to be.
Between each flattening and polishing step, the wafer is usually transferred to a different flattening/polishing station and cleaned or treated with chemicals. The wafer is transferred to different flattening and polishing stations since the different steps cannot be performed by (or at) a single station and the wafer is cleaned or treated with chemicals to reduce any undesired changes on the surface of the wafer, e.g., through oxidation that occurs when the wafer is exposed to oxygen and any other impurities that may have accumulated onto the surface of the wafer. The transferring and cleaning of the wafer results in a delay in the integrated circuit fabrication process and increases the overall costs. Additionally, the movement of the wafer in and out of the stations increases the probability of damage to the wafer.
A need has therefore arisen for a method and apparatus for flattening and polishing a semiconductor wafer that minimizes the need to move and to clean the wafer.
SUMMARY OF THE INVENTION
In one aspect, the present invention provides a polishing pad for use in polarization of semiconductor wafers comprising a polishing pad surface, a series of multifaceted appendages formed on the polishing pad surface, wherein each of the multifaceted appendages has a facet arranged orthogonal to a direction of movement of the polishing pad, and wherein each facet of the multifaceted appendages has an abrasive surface property, with each abrasive surface property of a single multifaceted appendage having a different abrasive property quality.
In another aspect, the present invention provides a method for planarizing a semiconductor wafer comprising the steps of moving a polishing pad having a series of multifaceted appendages in a first direction, applying the semiconductor wafer to the moving polishing pad, moving the polishing pad in a second direction, and applying the semiconductor wafer to the moving polishing pad.
The present invention provides a number of advantages. For example, use of a preferred embodiment of the present invention reduces or completely eliminates the need to move a semiconductor wafer between flattening and polishing stations, thereby speeding up the fabrication of the integrated circuits.
Also, use of a preferred embodiment of the present invention reduces the total number of flattening and polishing stations needed to prepare the semiconductor wafer. This reduces the costs involved in the preparation of the wafer and the overall cost of the fabrication of the integrated circuit.
Additionally, use of a preferred embodiment of the present invention reduces the physical handling and movement of the semiconductor wafer. By reducing the number of times that the wafer is handled, the chances of the wafer being damaged is also reduced.
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Infineon - Technologies AG
Morgan Eileen P.
Shakeri Hadi
Slater & Matsil L.L.P.
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