Semiconductor protection device

Details Semiconductor protection device Semiconductor protection device

2001-10-31

2003-04-08

Wilson, Allan R. (Department: 2815)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S355000

Reexamination Certificate

active

06545322

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to a semiconductor integrated circuit device. More particularly, the present invention relates to a field-effect semiconductor integrated circuit, in particular, ICs for a voltage regulator for step-up and down voltage, for voltage control, for liquid crystal drive, for thermosensible paper resistor drive, and the like.
2. Description of the Related Art
In a conventional semiconductor integrated circuit device shown in
FIG. 3
, there are provided a relatively long second minimum distance
22
, a relatively long third minimum distance
23
, and a relatively short first minimum distance
21
. The second minimum distance
22
is a distance between a gate electrode
11
side end in a channel length direction of a drain region
10
of a transistor composing an input-output circuit and an end of a contact region
12
that electrically connects the drain region
10
and a metal electrode
14
. The third minimum distance
23
is a distance between an end on the opposite side to the gate electrode
11
in the channel length direction and an end of the contact region
12
that electrically connects the drain region
10
and the metal electrode
14
. The first minimum distance
21
is a distance between an end in a channel width direction of the drain region
10
of the transistor composing the input-output circuit and an end of the contact region
12
that electrically connects the drain region
10
and the metal electrode
14
.
FIG. 2
shows an example of a transistor for an input-output circuit of a conventional semiconductor integrated circuit device.
FIG. 2
is a plan view of an insulated-gate field-effect transistor.
In the transistor shown in
FIG. 2
, each of a drain region
10
and a source region
13
, which are electrically isolated from each other by a gate electrode
11
connected electrically to metal electrodes
14
and
15
is provided with contact regions
12
, and the drain region
10
and the source region
13
are electrically connected to the metal electrodes
14
and
15
, respectively. Thus, desired electrical characteristics are obtained.
Since this transistor is connected directly to an input-output terminal
36
, external noise is applied directly to the transistor. Hence, the transistor has a characteristic of excellent external noise immunity. Conventionally, as a technique for obtaining this, it has been well known to increase a second minimum distance
22
, to increase a channel width, or to reduce the channel width.
In a semiconductor integrated circuit device shown in
FIG. 4
, a relatively long first minimum distance
21
is provided in a transistor used in an input-output circuit of a semiconductor integrated circuit composed of a plurality of field-effect transistors. The first minimum distance
21
is a distance between an end in the channel width direction of a drain region
10
and an end of a contact region
12
that electrically connects the drain region
10
and a metal electrode
14
.
FIG. 4
is a plan view of the transistor composing an input-output circuit of a semiconductor integrated circuit device.
In the transistor shown in
FIG. 4
, each of the drain region
10
and a source region
13
, which are electrically isolated from each other by a gate electrode
11
is provided with contact regions
12
, and the drain region
10
and the source region
13
are electrically connected to the metal electrodes
14
and
15
, respectively. Thus, desired electrical characteristics are obtained.
Since this transistor is connected directly to an input-output terminal
36
, external noise is applied directly to the transistor. Hence, the transistor has a characteristic of excellent external noise immunity.
In this case, since the first minimum distance
21
is provided so as to be longer than a second minimum distance
22
and a third minimum distance
23
, localization of overcurrent generated when electrostatic noise is applied to the drain region
10
is relieved. Thus, breakdown of the transistor due to local heat generation can be suppressed. Here, the first minimum distance
21
is a distance between the end in the channel width direction of the drain region
10
and an end of a contact region
12
that electrically connects the drain region
10
and the metal electrode
14
. The second minimum distance
22
is a distance between a gate electrode
11
side end in the channel length direction of the drain region
10
and an end of the contact region
12
that electrically connects the drain region
10
and the metal electrode
14
. The third minimum distance
23
is a distance between the end on the opposite side to the gate electrode
11
in the channel length direction and an end of the contact region
12
that electrically connects the drain region
10
and the metal electrode
14
.
Conventionally, as a technique for achieving this, it has been well known to increase the second minimum distance
22
or to increase the channel width. In the conventional technique, however, in order to obtain practically preferable electrostatic resistance, for example, a total width of transistors electrically connected to the same input-output terminal had to be at least about 200 &mgr;m even when the second minimum distance
22
between the gate electrode
11
side end in the channel length direction of the drain region
10
and an end of the contact region
12
in the drain region
10
and the third minimum distance
23
between the end on the opposite side to the gate electrode
11
and an end of the contact region
12
in the drain region
10
were set to be at least about 7 &mgr;m.
However, when the first minimum distance
21
between the end in the channel width direction of the drain region
10
and an end of the contact region
12
in the drain region
10
was set to be longer than the second and third minimum distances
22
and
23
, it was possible to reduce the total channel width of the transistors electrically connected to the same input-output terminal to 140 &mgr;m or less even when the second and third minimum distances
22
and
23
were about 7 &mgr;m. It also is possible to reduce the total channel width to about 120 &mgr;m or less, or about 100 &mgr;m or less, although it also depends on differences in mounting conditions or in device constructions and manufacturing process configurations. In addition, this effect further increases when the first minimum distance
21
is set to be longer than the second and third minimum distances
22
and
23
by about 1 &mgr;m. Furthermore, in the case where the phenomenon determining a static drain withstand voltage of this transistor is junction breakdown that occurs between the drain and the semiconductor substrate region
1
, the influence of the relationship between the first minimum distance
21
and the third minimum distance
23
on the electrostatic resistance further increases. When the phenomenon determining a static drain withstand voltage of this transistor is surface breakdown caused by the gate electrode
11
, the influence of the relationship between the first minimum distance
21
and the second minimum distance
22
on the electrostatic resistance further increases.
In the above, examples were described that were effective when power supply voltage is about 3 V or lower, about 5 V or lower, or about 7 V or lower. However, this technique provides the same effect when the power supply voltage is between about 7 V and about 40 V. In addition, a similar effect can be obtained even when the power supply voltage is about 40 V or higher.
However, for example, in the case of a transistor with a LDD structure having a side spacer on a side wall of a gate electrode
11
used when the power supply voltage or an applied electric field is high, the electrostatic resistance may increase in some cases when the second and third minimum distances
22
and
23
rather than the first minimum distance
21
are set to be longer.
This effect further increases when the static drain withstand voltages at the four periph

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