Electrical computers and digital data processing systems: input/ – Intrasystem connection – Bus interface architecture
Reexamination Certificate
1999-12-29
2003-08-26
Myers, Paul R. (Department: 2181)
Electrical computers and digital data processing systems: input/
Intrasystem connection
Bus interface architecture
Reexamination Certificate
active
06611893
ABSTRACT:
FIELD OF THE INVENTION
The invention pertains to electronic busses. More particularly, the invention pertains to arbitration of access to an electronic bus.
BACKGROUND OF THE INVENTION
The use of busses (e.g., address busses and data busses) to provide a single data path that is shared by a plurality of data processing devices, such as memories, microprocessors, micro controllers, digital signal processors (DSPs), and peripheral devices is, of course, well known. Busses are most commonly formed on printed circuit boards (PCBs) and interconnect a plurality of devices, for example, integrated circuits, mounted on the PCB. The busses may also run out to connectors, such as on a backplane of a personal computer, in order to allow peripheral devices to be coupled to the bus.
Busses on PCBs commonly are subject to substantial noise. Particularly, a bus is essentially a long metal wire which can be subject to a significant amount of capacitive coupling with other devices mounted or imprinted on the PCB.
Recently, integrated circuit manufacturers have begun producing single chips containing multiple device cores of the type, e.g., memories, micro controllers, DSPs, and microprocessors, that traditionally were embodied on different chips mounted on a PCB and interconnected by one or more busses that ran on the PCB. Such a chip is commonly termed a system-on-a-chip or SoC.
SoCs also frequently incorporate busses to provide data paths to interconnect the multiple core devices (sometimes called macro blocks or macros) on the chip. The busses on SoCs, however, comprise conductor traces on the chip and thus tend to be much shorter in length and less sensitive to noise than PCB busses. A typical SoC that would include one or more busses might be a SoC including a processor or multiprocessor that connects to several peripheral devices and/or several memory blocks (SRAM, DRAM, PROM and ROM).
Conventional busses on PCBs are usually quite long. Therefore, the data speed on such busses, i.e., the bus bandwidth, is limited as a function of the bus length. Specifically, the data rate on the bus cannot be made faster than the maximum amount of time it would take for data to travel from one end of the bus to the opposite end plus the maximum possible delay from enablement to data acquisition and the receive latch time. The speeds of data processing devices and memories have become so fast that the bus length is now commonly the bandwidth limiting factor for data transfer rates over PCB busses. For instance, microprocessors now commonly operate at speeds of 500 MHz and higher. However, the time for a signal to travel from one end of a PCB to another, e.g., 5 inches, might be on the order of 10 nanoseconds (10×10
−9
seconds). Accordingly, the bus bandwidth of such a bus would need to be limited to no greater than 100 MHz (1/(10×10
−9
seconds).
Busses that solely interconnect core devices on a SoC are much shorter in length and are not nearly as sensitive to noise as PCB busses. Accordingly, data transfer rates over SoC busses typically are not limited by the bus length, but by the speed of the core devices. Thus, the bus speed on a SoC commonly is limited to the data transfer speed of the slowest device coupled to the bus.
SUMMARY OF THE INVENTION
The invention is a method and apparatus for arbitrating access to a bus such that the bus can operate at a variable data rate and all data transfers over the bus require just one dedicated high speed bus clock cycle regardless of the speeds of the two devices (transmitter and receiver) involved in the transaction. Since only one dedicated bus clock cycle is used per transfer, the invention allows multiple device pairs to intersperse data transactions over the bus. Specifically, if no single device pair is capable of transferring data utilizing the full speed of the bus, one device pair can actively drive the bus during cycles that are not dedicated to transfers between another device pair, but that occur while the other device pair(s) is setting up its data for the bus.
The smart arbiter in accordance with the present invention has knowledge of the clock speeds and phases of the rot clocks of all of the devices that use the bus and grants accesses, issues bus grants and enables the corresponding output buffers at times based on that information in order to utilize only a single dedicated bus cycle per each transaction and to most efficiently utilize the bandwidth of the bus. The smart arbiter can intersperse grants such that data transfers between multiple pairs of transmitting and receiving devices that are not individually utilizing the maximum bandwidth capabilities of the bus can overlap. Thus, if one pair of devices is exchanging multiple words (or other units of data) at a rate slower than the maximum rate of the bus, another pair of devices can use some of the bus clock cycles between the transfer of words of the first device pair, for transfers of words between the second device pair.
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Lee Hyun
Potter David W.
Agere Systems Inc.
Myers Paul R.
Synnestvedt & Lechner LLP
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