Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2002-01-23
2003-04-15
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S700000, C438S715000, C438S725000
Reexamination Certificate
active
06548401
ABSTRACT:
TECHNICAL FIELD
The invention pertains to semiconductor processing methods and semiconductor constructions. In particular aspects, the invention pertains to dual-damascene processing methods, and to structures formed during dual-damascene semiconductor processing methods.
BACKGROUND OF THE INVENTION
Semiconductor processing frequently involves formation of an electrical contact to a conductive structure. For instance, semiconductor devices frequently comprise a substrate having numerous electrical components supported therein and thereover, and above the electrical components are provided one or more metal layers. The metal layers can electrically connect the components to one another, and can be further utilized to electrically connect circuitry associated with a semiconductor device to other circuitry external of the device. The metal layers can be referred to as a metal I layer, metal II layer, metal III layer, metal IV layer, etc; with the numeric designation indicating the approximate level of the metal layer relative to the semiconductor circuit components. For instance, the first metal layer formed over the components will typically be referred to as a metal I layer, and the various other layers formed over the metal I layer will be numbered in ascending, sequential order. Electrical contacts are ultimately to be formed to electrically connect the various metal layers to one another, as well as to electrically connect the metal layers with the circuit components of the semiconductor device.
One method of forming electrical interconnects between elevationally separated conductive components is a damascene process. An exemplary damascene process is described with reference to
FIGS. 1-5
.
Referring initially to
FIG. 1
, a fragment of a semiconductor construction
10
is illustrated. The fragment comprises a semiconductor substrate
12
having an insulative mass
14
thereover. Substrate
12
can comprise, for example, monocrystalline silicon. To aid in interpretation of the claims that follow, the terms “semiconductive substrate” and “semiconductor substrate” are defined to mean any construction comprising semiconductive material, including, but not limited to, bulk semiconductive materials such as a semiconductive wafer (either alone or in assemblies comprising other materials thereon), and semiconductive material layers (either alone or in assemblies comprising other materials). The term “substrate” refers to any supporting structure, including, but not limited to, the semiconductive substrates described above. In exemplary constructions, substrate
12
can comprise various conductive, semiconductive, and insulative semiconductor device components (not shown), in addition to monocrystalline silicon.
Insulative mass
14
can comprise, for example, borophophosilicate glass (BPSG).
A conductive structure
16
is illustrated to be supported within insulative mass
14
. Conductive structure
16
can comprise a semiconductor device component, or alternatively can comprise a metal layer, such as, for example, a metal I layer.
A patterned masking material
18
is formed over insulative mass
14
. Masking material
18
can comprise, for example, photoresist, and can be patterned into the shown shape utilizing photolithographic processing methods. Patterned masking material
18
has an opening
20
extending therethrough, which exposes a portion of insulative mass
14
.
Referring to
FIG. 2
, the exposed portion of insulative mass
14
is removed to extend opening
20
to conductive structure
16
.
Referring to
FIG. 3
, masking layer
18
(
FIG. 2
) is removed, and a sacrificial, protective material
22
is formed across an upper surface of mass
14
and within opening
20
. Material
22
can comprise, for example, anti-reflective coating (ARC) materials, such as, for example, bottom anti-reflective coating (BARC) materials. An exemplary BARC is DUV 42P, available from Brewer Science Corporation. Material
22
can be considered to comprise a first portion on an upper surface of mass
14
, and a second portion within opening
20
.
After formation of protective material
22
, a patterned masking layer
24
is formed over the first portion of material
22
. Masking layer
24
can comprise, for example, photoresist, and can be patterned by photolithographic processing. Material
24
defines a second opening
26
which overlaps with the first opening
20
.
Referring to
FIG. 4
, an etch is conducted to extend second opening
26
through the first portion of protective material
22
and into mass
14
. The second portion of material
22
within opening
20
protects conductive structure
16
from being exposed to the etching conditions. A difficulty can occur during the etch in attempting to remove the first portion of protective material
22
that is over mass
14
. Specifically, it is difficult to find an etch which is selective for ARC or BARC relative to photoresist masking layer
24
, and accordingly some of the masking layer
24
is removed during the etch. Such removal of masking layer
24
is illustrated by dashed lines
28
which show the starting position of material
24
, and illustrate that material
24
has retreated from opening
26
during the etch of material
22
. Such causes a widening of opening
26
, and hence an increase in the critical dimension of opening
26
. The widening of opening
26
also decreases a space between opening
26
and an adjacent opening or feature (not shown). A continuing goal in semiconductor processing is to reduce a footprint of various devices relative to a semiconductor substrate in order to conserve valuable semiconductor real estate. The increase in the critical dimension of opening
26
is therefore not desired.
Referring to
FIG. 5
, materials
22
and
24
(
FIG. 4
) are removed from over mass
14
and conductive structure
16
. A difficulty can occur in removing BARC and ARC materials, in that polymers can be formed which deposit over conductive material
16
, and which are difficult to selectively remove relative to conductive material of structure
16
. For instance, structure
16
will frequently comprise, consist essentially of, or consist of copper; and it can be difficult to remove polymatic materials relative to copper without having at least some etching into the copper. The etching into the copper can detrimentally effect performance of circuitry utilizing conductive structure
16
.
After removal of materials
22
, and
24
, the openings
20
and
26
can be filled with a suitable conductive material (not shown) to form an interconnect to conductive structure
16
. In particular embodiments, opening
20
will be a via which extends to conductive structure
16
, and opening
26
will be a slot. Accordingly, conductive material formed within openings
26
and
20
comprises a conductive line within slot
26
which is electrically connected to conductive structure
26
through a conductive interconnect defined by the conductive material formed within via
20
.
SUMMARY OF THE INVENTION
In one aspect, the invention encompasses a dual-damascene semiconductor processing method. A semiconductor substrate is provided. The substrate includes a conductive structure and an insulative layer over the conductive structure. A via is etched through the insulative layer and into the conductive structure, and a resist is formed within the via. A material is formed over the resist and substrate. A portion of the material in contact with the resist is hardened, and another portion of the material that does not contact the resist is not hardened. The portion of the material which is not hardened is removed, and a slot is etched into the insulative layer. The resist and hardened portion of the material protect the conductive structure during the etching of the slot.
In another aspect, the invention encompasses a semiconductor processing method in which a first opening is formed to extend into a substrate. The first opening has a periphery at least partially defined by the substrate. A mass is formed within the first opening to only partially
Chaudhuri Olik
Lee Hsien-Ming
Micro)n Technology, Inc.
Wells St. John P.S.
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