Passgate structures for use in low-voltage applications

Details Passgate structures for use in low-voltage applications Passgate structures for use in low-voltage applications

2001-08-16

2003-12-09

Tran, Anh (Department: 2819)

Electronic digital logic circuitry

Multifunctional or programmable

Array

C326S038000, C326S047000, C326S101000

Reexamination Certificate

active

06661253

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to integrated circuit devices, and more particularly to the passgate structures which may be used in such devices.
One of the most ubiquitous structures within an integrated circuit device is the single-transistor passgate, which is commonly used to implement (either singly or in combination with other circuits) switches, multiplexers, logic functions (e.g., pass transistor logic), and gating mechanisms for tristatable circuits (e.g., buffers and drivers). In some integrated circuit devices, single-transistor passgate structures may account for a significant portion of the circuitry; for example, in the case of programmable logic devices, single-transistor passgates are used extensively throughout the device as part of the programmable interconnection circuitry.
The operation of a typical single-transistor passgate may be succinctly illustrated by a description of an NMOS passgate (analogous principles of operation, as understood by one skilled in the art, would apply for a PMOS passgate). Depending on whether the potential difference between its gate terminal, V
GATE
, and its source terminal, V
SOURCE
, exceeds the threshold voltage, V
t
, an NMOS passgate acts as an “open” or a “closed” switch. (As is well-known in the art, there is no physical difference between the “source” and “drain” terminals of an MOS device; the source terminal of an NMOS transistor is the terminal having the lower voltage.) When V
GATE
−V
SOURCE
is less than V
t
, the NMOS passgate is in the “cutoff” state, thereby acting as an “open” switch; when V
GATE
−V
SOURCE
is greater than V
t
, the NMOS passgate is in the conduction state, thereby acting as a “closed” switch.
Accordingly, a ceiling is imposed on the output of an NMOS passgate in that it cannot exceed V
GATE
−V
t
(since the NMOS passgate starts to enter the “cutoff” mode when V
GATE
−V
SOURCE
approaches V
t
). For example, when V
GATE
and a logic HIGH signal to be passed by an NMOS passgate both correspond to the positive supply level, V
DD
, the signal that may be passed to the output of the NMOS passgate is limited to V
DD
−V
t
. Extending the analysis to the case of PMOS passgates, a lower limit equal to |V
t
| is imposed on logic LOW signals that may be passed. (As is well-known in the art, V
t
is not a discrete value for an MOS transistor; it may be considered a range of values that is influenced by a variety of second-order effects, such as substrate bias and subthreshold conduction. However, in order to simplify the illustration of the principles of the present invention, V
t
will be discussed herein as if it is a discrete value rather than a range of values.)
With the current trend in scaling down device geometries and the consequent use of ever-lower operating voltages (e.g., supply voltages, bias voltages, etc.), which are nearing levels comparable to V
t
, the ability of single-transistor passgate structures to reliably pass recognizable logic levels will become more difficult in view of the influence V
t
exerts on the logic levels that may be propagated (i.e., the V
GATE
−V
t
ceiling imposed on the logic HIGH voltage levels that are passed by NMOS passgates, and the |V
t
| lower limit on the logic LOW signals that are passed by PMOS passgates).
SUMMARY OF THE INVENTION
The present invention relates to enhanced passgate structures for use in low-voltage systems. In accordance with the principles of the present invention, various techniques are presented for mitigating the effect of V
t
on the range of signals that may be propagated through single-transistor passgates. Although the techniques described herein are illustrated using NMOS passgates, they may be readily adapted to PMOS structures.
In one arrangement, the V
GATE
−V
t
limit imposed on the logic HIGH signals passed by NMOS passgates may be raised by applying higher V
GATE
levels, which may be provided from a variety of sources. Alternatively, the V
GATE
−V
t
ceiling may be raised by lowering V
t
via process adjustments during fabrication and/or by tuning the biasing voltage of the well in which the passgate is fabricated.
Also, the use of CMOS passgates in applications where single-transistor passgates have traditionally been used is presented.


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patent: 5574634 (1996-11-01), Parlour et al.
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APEX 20K Programmable Logic Device Family, Data Sheet, Mar. 2000, ver. 2.06, Altera Corporation, pp. 1-208.
FLEX 8000 Programmable Logic Device Family, Data Sheet, Jun. 1999, ver. 10.01, Altera Corporation, pp. 349-410.
FLEX 10K Embedded Programmable Logic Family, Data Sheet, Jun. 1999, ver. 4.01, Altera Corporation, pp. 1-137.
XC3000 Series Field Programmable Gate Arrays (XC3000A/L, XC3100A/L), Product Description, Nov. 9, 1998, ver. 3.1, Xilinx, Inc., pp. 7-3 through 7-78.

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