Electrical computers and digital processing systems: memory – Storage accessing and control – Hierarchical memories
Reexamination Certificate
2001-05-07
2003-06-03
Nguyen, Hiep T. (Department: 2187)
Electrical computers and digital processing systems: memory
Storage accessing and control
Hierarchical memories
C711S105000, C711S202000, C711S146000, C711S217000, C711S218000, C711S219000, C365S230040, C365S233100, C365S236000
Reexamination Certificate
active
06574707
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to semiconductor memory devices, and more specifically, to memory interfaces between a processor and a memory.
BACKGROUND OF THE INVENTION
Conventional caches typically request information from a main memory in the form of a bursting Flash memory in response to a request from a processor. When information is requested from main memory, it is stored in lines of the cache in words that may be of arbitrary size. Cache lines containing multiple word information typically store the information in sequentially ordered words. A processor requests a particular word from its cache. When reading the requested information from a cache line, the processor will always desire only the requested word. However, the requested (i.e. most critical) word may or may not be a first word of a cache line. Should information requested by the processor not be contained within the cache, this situation is termed a “miss”. The address of the requested word is then provided to the main memory for subsequent retrieval of the requested word. If the critical word of a cache line desired by the processor is not the first word, the cache line must be written to in a wrap fashion to back fill the first portion of the line prior to the critical word. Such information addressing is commonly known as a wrap around mode because in order for the line of information being written to the cache to be valid, all information words must be written to the cache line.
A disadvantage with the wrap around addressing mode is that main memories are designed to repeat the information for the same cache line until another initial access is made of the main memory. An initial access requires several clock cycles to get the information and reestablish proper timing. At least one initial main memory access must occur for every cache line that is retrieved. An initial main memory access typically involves: (1) broadcasting an address to the main memory; (2) sending a signal to the main memory informing the main memory that a new address has appeared; (3) decoding the new address by the main memory; (4) locate the information and use sense amplifiers to detect the logic value of each bit of information; and (5) capture and output the information. Therefore, the total overhead for each cache line fill, even in a burst memory system, is substantial and leads to significant performance delays.
Another addressing technique that may be implemented is known as linear addressing. In this technique, a cache line is always filled by a main memory from a first word to last word. The addressing is simple as information retrieval always begins from a beginning of a cache line. However, should a critical word desired by a data processor be a last word in a cache line, a severe performance penalty occurs in systems implementing longer cache lines.
Main memories are typically designed to support only one mode of addressing. Prior to being operational, a user must carefully follow specific mode programming instructions to place the main memory in an operation mode which will support either linear or wrap around addressing. Some commercially available memories do not support both modes. However, those memories that do provide a user with an addressing option function by remaining in the same addressing mode unless the programming procedure is repeated. Repeating the programming procedure to modify addressing modes is typically not feasible once a memory is initialized into a functional system.
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Clingan, Jr. James L.
Dinh Ngoc
King Robert L.
Motorola Inc.
Nguyen Hiep T.
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