Static information storage and retrieval – Read/write circuit – Including reference or bias voltage generator
Reexamination Certificate
2000-08-28
2003-08-19
Tran, M. (Department: 2818)
Static information storage and retrieval
Read/write circuit
Including reference or bias voltage generator
C365S185270
Reexamination Certificate
active
06608781
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a nonvolatile semiconductor memory device and a programming method therefor, and relates in particular to a nonvolatile semiconductor memory device (a flash memory) and a programming method therefor.
2. Description of Related Arts
At present, various types of nonvolatile semiconductor memory devices, such as mask ROMs, EEPROMs and flash memories, are available. Of these devices, an electrically rewritable flash memory that is appropriate for high integration has drawn the attention of many people (see Japanese Unexamined Patent Publication No. Hei 6-275842). For nonvolatile memory, in principle, one transistor constitutes one memory cell, and since basically no selection transistors are required and a memory cell occupies only a small area, originally the data held by a single memory cell could not be erased. Now, however, with flash memory, data erasing is performed collectively by blocks.
Memory cells (a circuit) in a flash memory are shown in FIG.
11
. In
FIG. 11
, a source voltage Vs and a substrate voltage Vb are used in common by four memory cells M
00
, M
01
, M
10
and M
11
. The control gates of the memory cells M
00
and M
01
are connected in common to a row line W
0
while the control gates of the memory cells M
10
and M
11
are connected in common to a row line W
1
, and the drain electrodes of the memory cells M
00
and M
10
are connected in common to a column line D
0
while the drain electrodes of the memory cells M
01
and M
11
are connected in common to a column line D
1
.
The threshold value of each memory cell, viewed from its control gate, differs, depending on whether electrons have accumulated at its floating gate. That is, when no electrons have accumulated at a cell's floating gate, the threshold value viewed from its control gate is reduced, and when electrons have accumulated at the cell's floating gate, the threshold value viewed from its control gate is increased. This cell characteristic makes the nonvolatile storage of information possible.
An explanation will now be given, while referring to
FIG. 17
, of the voltages that are applied to the electrodes of the memory cell M
00
in
FIG. 11
during the data reading, the data programming (writing) and the data erasing processes.
First, when data are to be read from the memory cell M
00
, as is shown in
FIG. 17
the voltage set for the row line W
0
is 5 V, for the row line W
1
is 0 V and for the column line D
0
is 1 V, while the column line D
1
is open and the voltage set for both the source voltage Vs and the substrate voltage Vb is 0 V. Thus, upon the application of 5 V to the control gate of the memory cell M
00
and 1 V to the drain, the memory cell transistor is rendered conductive if the threshold value of the memory cell M
00
is low (equal to or below 5 V), or is rendered non-conductive if the threshold value of the memory cell M
00
is high (above 5 V). The conductive
on-conductive control is performed in accordance with whether a reading circuit (not shown) detects the flowing of a drain current.
When the memory cell M
00
is to be programmed, as is shown in
FIG. 17
the voltage set for the row line W
0
is 10 V, for the row line W
1
it is 0 V and for the column line D
0
it is 6 V, while the column line D
1
is open and the voltage set for both the source voltage Vs and the substrate voltage Vb is 0 V. Thus, since a voltage of 10 V is applied to the control gate of the memory cell M
00
and a voltage of 6 V is applied to the drain, a hot carrier is injected into the floating gate of the memory cell M
00
, and the threshold value of the memory cell M
00
is increased as described above.
For erasing data, there are a “substrate erasing method,” for discharging, to the substrate, the electrons accumulated at the floating gate, and a “source-gate erasing method,” for discharging the accumulated electrons to the source. According to the substrate erasing method, as is shown in
FIG. 17
the voltage set for both the row lines W
0
and W
1
is −10 V, while the column lines D
0
and D
1
and the source voltage Vs are open and the voltage set for the substrate voltage Vb is 10 V. Thus, since a voltage of −10 V is applied to the control gate of each memory cell while a voltage of 10 V is applied to the substrate, the electrons accumulated at the floating gate are discharged to the substrate, and not only are the data in the memory cell M
00
erased, but the data in all the other memory cells are also erased, collectively. According to the source-gate erasing method, as is shown in
FIG. 17
the voltage set for both the row lines W
0
and W
1
is −10 V, while the column lines D
0
and d
1
are open and the voltage set for both the source voltage Vs and the substrate voltage Vb is 10 V. Thus, since a voltage of −10 V is applied to the control gate of each memory cell and a voltage of 10 V is applied to the source, the electrons accumulated at the floating gate are discharged to the source, and data in all the memory cells are collectively erased.
The substrate erasing method and the source-gate erasing method differ greatly in that, for the substrate erasing method, the substrate voltage Vb must be a positive high voltage, while for the source-gate method, the substrate voltage Vb is 0 V both for data programming and for data erasing. This difference is reflected in the device structures used for the two methods.
That is, the device structure appropriate for the substrate erasing method is as shown in
FIG. 12
, and the device structure appropriate for the source-gate erasing method is as shown in FIG.
13
.
In the structure in
FIG. 12
, an N well
2
is formed in a P semiconductor substrate
1
, a P well
3
is formed in the N well
2
, and a memory cell is formed in the P well
3
. An N diffusion layer
4
is formed in the N well
2
, while a P diffusion layer
5
, an N source diffusion layer
6
and an N drain diffusion layer
7
are formed in the P well
3
. A floating gate
8
and a control gate
9
are provided above a channel between the N source diffusion layer
6
and the N drain diffusion layer
7
. The individual regions are defined by field insulating films
10
.
Since with this arrangement a positive voltage can be applied to the substrate, this structure is appropriate for the substrate erasing method.
In the structure in
FIG. 13
, the N well
2
and the P well
3
are not included, and a memory cell transistor is formed directly in a P semiconductor substrate
1
. Since with this arrangement a positive voltage can not be applied to the substrate, this structure is appropriate for the source-gate erasing method. In this structure, a voltage of 0 V is constantly applied to the substrate.
According to either method, since as is described above the erasing of data is performed collectively for a plurality of memory cells, the erasing level differs for each memory cell. This means variances in the threshold voltages of the memory cells are produced after the data are erased, and a negative threshold value may be held by some memory cells.
As is described above, information is stored in a memory cell in accordance with whether during the reading process the threshold value held by the pertinent memory cell is equal to or lower than the row line voltage. Since in a flash memory a selection transistor is not provided for each memory cell, the threshold value must, at the least, be positive. If the threshold value is negative, the memory cell is rendered conductive, even when it is not selected, and selecting the memory cell is a meaningless effort.
Specifically, when the threshold value of a memory cell falls and becomes negative, during the reading process, deterioration of the reading characteristic occurs. Assume that the threshold value of the memory cell M
10
in
FIG. 11
falls and becomes negative, and that data are to be read from the memory cell in the programmed state (the cell has a high threshold value). Since the memory cell M
00
is in the progr
Jinbo Toshikatsu
Watanabe Kazuo
McGinn & Gibb PLLC
NEC Electronics Corporation
Tran M.
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