System for prioritizing slave input register to receive data tra

Details System for prioritizing slave input register to receive data tra System for prioritizing slave input register to receive data tra

1997-02-25

1999-08-17

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output access regulation

710 3, 710 31, 710 41, G06F 1318

Patent

active

059387467

ABSTRACT:
A master (1) and a slave (3) are connected via a transmission line (5) for sending a clock CL; another transmission line (6) for bidirectionally sending data DT; and still another transmission line (7) for sending a control signal CE. Having turned a control signal CE into "L," the master (1) transmits an address code as data DT to the slave (3). Referring to the content of the transmitted address code, the slave (3) detects whether it is a data transmission from the master (1) to the slave (3) or vice versa. While a control signal CE remains "H," data transmission takes place. Data output from the slave (3) to the data line (6) is managed by a bus driver (22). The bus driver (22) is turned off during a period from when the clock CL became "H" to when a control signal CE becomes "L" after data transmission so that data transmission from the master (1) will not be adversely affected.

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