Electronic digital logic circuitry – Interface – Supply voltage level shifting
Reexamination Certificate
1999-10-05
2003-08-12
Tokar, Michael (Department: 2819)
Electronic digital logic circuitry
Interface
Supply voltage level shifting
C326S063000, C326S068000, C326S062000, C327S333000
Reexamination Certificate
active
06605963
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, including a circuit unit having a predetermined function such as a level shifter circuit or a driver transistor circuit produced by combining a plurality of transistors, and a source potential switching method for the transistors in the semiconductor integrated circuit.
Especially in the case of a semiconductor integrated circuit configured as a MOS transistor such as an N-channel MOS transistor (hereinafter referred to as an N-ch transistor) or a P-channel MOS transistor (hereinafter referred to as a P-ch transistor), a higher integration and a miniaturization of the semiconductor integrated circuit have been advancing rapidly, and the requirement for a lower voltage of the voltage source and a lower power consumption of the semiconductor integrated circuit tends to increase at present. On the other hand, in order to realize a high operating speed of the semiconductor integrated circuit, a lower threshold voltage between the gate and the source of the MOS transistor is required.
2. Description of the Related Art
Assume that in order to realize the higher integration and miniaturization of the semiconductor integrated circuit as described above, the gate oxide film thickness of the MOS transistor is reduced to 1/k (k: positive number that is equal to 1 or more than 1). In the case in which the durability of the insulation of the gate oxide film remains unchanged, an electric field applied between both terminals of the gate oxide film is required to be constant so as to avoid the dielectric breakdown of the gate oxide film. For this to be achieved, the voltage of the power supply is also required to be reduced to 1/k. In order to realize a high operating speed of the semiconductor integrated circuit, on the other hand, the threshold voltage between the gate and the source of the MOS transistor is also desirably reduced to 1/k. A decreased threshold voltage, however, makes it impossible to cut off the current flowing between the source and the drain, thereby increasing the sub-threshold current during the standby period when the semiconductor integrated circuit is in a standby state.
In order to facilitate understanding of the problems encountered by the increased sub-threshold current during the standby period of a semiconductor integrated circuit such as a conventional level shifter circuit requiring a low-voltage, high-speed operation, the relationship between the voltage between the gate and the source and the sub-threshold current of an ordinary MOS transistor and the configuration and the operation of a conventional level shifter circuit will be explained below with reference to
FIGS. 1
to
3
that will be hereinafter described in “BRIEF DESCRIPTION OF THE DRAWINGS”.
The graph of
FIG. 1
shows the relationship between the voltage between the gate and the source and the current flowing between the source and drain of an ordinary MOS transistor.
In
FIG. 1
, assuming that Vgs is the voltage between the gate and the source and Ids is the current flowing between the source and the drain of the N-channel transistor in the MOS transistor (abbreviated to N-ch transistor in FIG.
1
), the relationship between the voltage between the gate and the source Vgs and the logarithmic value (log(Ids)) of the current Ids is illustrated. Assuming that the voltage Vgs for log(Ids)=I
0
is the threshold voltage between the gate and the source, for example, the threshold voltage of the first N-ch transistor {circle around (
1
)} is given as Vth and the threshold voltage of the second N-ch transistor {circle around (
2
)} is Vth′. Generally, the current Ids in a region in which the voltage Vgs is lower than the threshold voltage, i.e., the current Ids with the N-ch transistor in an off state (deactivated state) is called the sub-threshold current.
On the other hand, assume that the current for the voltage Vgs=0 V in the first N-ch transistor {circle around (
1
)} is Idso and the current for the voltage Vgs=0 V in the second N-ch transistor {circle around (
2
)} is Idso′. As shown in
FIG. 1
, suppose that the threshold voltage of the second N-ch transistor {circle around (
2
)} is lower than the threshold voltage of the first N-ch transistor {circle around (
1
)}, the currents (Idso and Idso′) for the voltage Vgs of 0 V are larger for the second N-ch transistor {circle around (
2
)} than for the first N-ch transistor {circle around (
1
)}. The ordinate of the graph of
FIG. 1
is in a logarithmic scale (log scale). Thus, the current for the voltage Vgs of 0 V increases by several orders of magnitude. In the case in which a negative bias voltage (−V′, for example) is applied as the voltage Vgs, however, the sub-threshold current remarkably decreases. Even though the absolute value of the negative bias voltage −V′ may be small, the effect of the negative bias voltage is large since the ordinate of this graph is in a logarithmic scale.
The graph of
FIG. 1
shows the relationship between the voltage Vgs and the current Ids flowing between the source and the drain of a N-ch transistor. The same can be said of a P-channel transistor (abbreviated to P-ch transistor in
FIG. 1
) except that the polarities of the voltage Vgs and the current Ids in the P-ch transistor are opposite to those in the N-ch transistor.
Generally, as the threshold voltage between the gate and the source of the MOS transistor is reduced, the sub-threshold current tends to increase. The sub-threshold current increases in proportion to the ratio (W/L) of the gate width to the gate length of the MOS transistor. Further, as a larger storage capacity, a higher integration and a miniaturization of a semiconductor integrated circuit have been advanced, the total gate widths W of a plurality of MOS transistors formed in the whole semiconductor chip constituting the semiconductor integrated circuit tend to increase. Because of the above-mentioned tendencies, the magnitude of the sub-threshold current has become not negligible.
In order to reduce the sub-threshold current during the standby period, the following protective method has been employed in the prior art. For a word decoder with the large total gate widths of the transistors, as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 6-203558, a method has been employed for reducing the gate width (W) of the transistor connected to a power supply by inserting a transistor having the small gate width between the power supply and a circuit.
Further, as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 5-108194, a method has been employed for reducing the current during the standby period by differentiating the bias of the well or the substrate between the activated period when the semiconductor integrated circuit is activated and the standby period during which the semiconductor integrated period is in a standby state.
Furthermore, as disclosed in Japanese Unexamined Patent Publication (Kokai) No. 7-38417, a method has been employed in which a resistor or a switching element is inserted between the MOS transistor constituting an inverter and a power supply thereby to impose a negative bias on the MOS transistor, or in which transistors of different threshold values and power supplies of different potentials are used during the activated period and the standby period.
Now, with regard to a level shifter circuit in which the input signal potential is required to be changed at high speed with a low voltage power supply, an explanation will be given of the relationship between the threshold voltage between the gate and source of the MOS transistor and the sub-threshold current.
FIG. 2
is a circuit diagram showing a configuration of a first example of a conventional level shifter circuit. The level shifter circuit shown in
FIG. 2
is disclosed in U.S. Pat. No. 4,486,670.
In the level shifter circuit
100
shown in
FIG. 2
, in order to produce an output signal OUT by converti
Eto Satoshi
Hasegawa Masatomo
Ishii Yuki
Kanou Hideki
Kawabata Kuninori
Armstrong Westerman & Hattori, LLP
Fujitsu Limited
Tan Vibol
Tokar Michael
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