Memory controller including write posting queues, bus read contr

Details Memory controller including write posting queues, bus read contr Memory controller including write posting queues, bus read contr

1997-03-05

1999-08-17

Lee, Thomas C.

Electrical computers and digital data processing systems: input/

Input/output data processing

Input/output command process

710 6, 710 55, 710107, 710112, 711155, G06F 1300, G06F 1314

Patent

active

059387394

ABSTRACT:
A memory controller which provides a series of queues between the processor and the PCI bus and the memory system. Memory coherency is maintained in two different ways. Before any read operations are accepted from the PCI bus, both of the posting queues must be empty. A content addressable memory (CAM) is utilized as the PCI to memory queue. When the processor performs a read request, the CAM is checked to determine if one of the pending write operations in the PCI to memory queue is to the same address as the read operation of the processor. If so, the read operation is not executed until the PCI memory queue is cleared of the write. To resolve the problem of aborting a Memory Read Multiple operation, an abort signal from the PCI bus interface is received and as soon thereafter as can be done the read ahead cycle is terminated, even though the read ahead cycle has not fully completed. The memory controller has improved prediction rules based on whether the cycle is coming from the processor or is coming from the PCI bus to allow more efficient precharging when PCI bus cycles are used. The memory controller is highly programmable for multiple speeds and types of processors and several speeds of memory devices.

REFERENCES:
patent: 4888739 (1989-12-01), Frederick et al.
patent: 5125083 (1992-06-01), Fite et al.
patent: 5155843 (1992-10-01), Stamm et al.
patent: 5222223 (1993-06-01), Webb, Jr. et al.
patent: 5224214 (1993-06-01), Rosich
patent: 5379379 (1995-01-01), Becker
patent: 5432918 (1995-07-01), Stamm
patent: 5471591 (1995-11-01), Edmondson et al.
patent: 5471598 (1995-11-01), Quattromani
patent: 5499384 (1996-03-01), Lentz et al.
patent: 5535341 (1996-07-01), Shah et al.
patent: 5596729 (1997-01-01), Lester et al.
patent: 5613075 (1997-03-01), Wade et al.
patent: 5666494 (1997-09-01), Mote, Jr.
Intel DX4 Processor Data Book, Intel Corp., pp. i-ii, 7-12 to 7-21, 8-29 to 8-32 (Feb. 1994).
Intel Pentium Processor User's Manual, vol. 1; Pentium Processor Data Book, pp. i-iii, 6-28 to 6-30 (1994).
Motorola Semiconductor Technical Data: 32K X 9 Bit Burst RAM, Synchronous Static RAM, pp. 4-10 to 4-19 (1993).
Intel 82420/82430 PCIset ISA and EISA Bridges, p. 345, 482-483, (Apr. 1993).
Intel 82430 PCIset Cache/Memory Subsystem, pp. 15-25 (Mar. 1993).
PCI Local Bus Specification Production Version, Rev. 2.0, Apr. 1993, pp. 19-22, 25-36, 51-52, 69-78.

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