Error detection/correction and fault detection/recovery – Data processing system error or fault handling – Reliability and availability
Reexamination Certificate
2000-03-06
2003-06-10
Baderman, Scott (Department: 2184)
Error detection/correction and fault detection/recovery
Data processing system error or fault handling
Reliability and availability
C714S006130, C714S710000
Reexamination Certificate
active
06578157
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to the use of partially defective direct Rambus DRAM (“RDRAM”) chips. More particularly, the present invention relates to the recovery of RDRAM components that do not have all memory areas accessible by appropriately configuring a plurality of the defective RDRAM components to simulate the operation of a fully operational RDRAM chip.
2. State of the Art
As is well known in the art, during the production of monolithic memory devices from silicon wafers, some of the memory storage cells can become unreliable or fail to function altogether. These defective cells can be the result of a number of causes such as impurities introduced in the process of manufacturing the monolithic memory device from the silicon wafer, or localized imperfections in the silicon substrate itself. As used herein, the term “silicon” is intended to encompass all semiconductor materials.
Often, while some memory cells are defective, many other cells on the same memory chip are not defective and will work reliably and accurately. Additionally, it is often the case that the defective cells are localized and confined to particular connections from the memory device. The remaining non-defective connections can be relied upon to provide a consistent and accurate representation of the information in the storage cell. Testing procedures well known in the art are performed to determine how many, and which, cells within a memory chip are good or accessible and how many, and which, are defective. In this way it can readily be determined and mapped which DQ connectors reliably send and receive accurate and valid data to and from which non-defective cells.
Techniques have been developed for salvaging the non-defective portions of defective asynchronous memory technologies (e.g., DRAM). Asynchronous memory technologies are relatively slow devices that operate in response to control signals generated by a memory controller, rather than in response to the system clock. The control signals allow the asynchronous memory device to operate at a speed that is much slower than the system clock, which ensures reliable read and write memory operations.
Techniques have also been developed for salvaging non-defective portions of some forms of synchronous memory technologies such as SDRAM. SDRAM devices are much faster than asynchronous devices principally because SDRAM is capable of synchronizing itself with the microprocessor's clock. This synchronization can eliminate the time delays and wait states often necessary with prior memory technologies (e.g., DRAM), and allows for fast, consecutive read and write capability.
Synchronous memory devices such as Rambus DRAM “RDRAM” include a data bus architecture which departs from the backplane bus architecture typical in prior DRAM and SDRAM systems. U.S. Pat. No. 5,513,327 (Farmwald et al.), the disclosure of which is hereby incorporated herein by reference, describes the differences in the structure and function of RDRAM versus prior art SDRAM and DRAM.
However, no attempts known to the inventors have been made to date to salvage non-defective portions of partially defective RDRAM devices. Some people skilled in the art believe that the use of known techniques for salvaging defective memory devices would not work to salvage RDRAM components because RDRAM operates at much higher speeds than previous memory devices (presently up to 800 Mb/s per pin or 1.6 GB/s per device).
SUMMARY OF THE INVENTION
The present invention addresses the problem of salvaging partially defective RDRAM devices. In one embodiment of the present invention, a plurality of partially defective RDRAM devices is placed in a parallel configuration, assigned the same device ID numbers and substituted for a single non-defective RDRAM device during fabrication of a memory module to simulate that single non-defective RDRAM device. Defective DQ connectors may also be left unconnected to, or separated from, corresponding data lines such that each data line is only connected to one non-defective DQ connector of the plurality of partially defective RDRAM devices.
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Howarth James J.
Larsen Corey L.
Weber Richard R.
Baderman Scott
Lohn Joshua
Micro)n Technology, Inc.
TraskBritt
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