Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2001-03-12

2003-07-29

Smith, Matthew (Department: 2825)

Computer-aided design and analysis of circuits and semiconductor

Nanotechnology related integrated circuit design

C716S030000, C716S030000, C716S030000

Reexamination Certificate

active

06601218

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device and a technique for manufacturing the semiconductor integrated circuit device, and more particularly to a design for testability capable of reducing an over-head caused by having a test circuit in the semiconductor integrated circuit device, for example, an effective technique to be applicable to a semiconductor integrated circuit such as a system LSI (Large Scale Integrated Circuit) having a RAM (Random Access Memory) provided therein.
BACKGROUND OF THE INVENTION
In general, as a general design for testability in a logic LSI referred to as a system LSI having a RAM, a CPU and the like mounted thereon, there has been often used a scanning path methodology in which a flip-flop constituting an internal logic circuit is serially connected to input test data and the internal logic circuit is operated to check a logic status. Ten years or more have passed since this technology has been proposed as an LSSD (Level Sensitive Scan Design) method, and furthermore, this technology has an over-head of approximately 35% for hardware and a fault coverage of approximately 85%. There has been a problem in that a great deal of endeavor is required to increase the coverage still more.
In order to increase the fault coverage, moreover, it is necessary to remarkably increase the pattern capacity of a test pattern generator provided in a tester. Consequently, the price of the tester is increased considerably. Furthermore, test data should be input as serial data. Therefore, a great deal of time is required to input a test pattern. Therefore 50% or more of a test time is required for inputting the test pattern so that the effective availability of the tester is also reduced.
In addition to the scanning path methodology, there has been a BIST (Built-In Self Test) methodology in which a random pattern generator and a signature compression circuit are mounted on a chip as test circuits. The BIST methodology uses a random test pattern differently from logic testability based on a test pattern generated in accordance with a fault coverage algorithm to be used for the scanning path methodology. For this reason, whether or not a proper fault coverage is maintained is a big problem, and various techniques are to be developed to obtain an appropriate methodology.
Also in the case in which the BIST methodology is employed, furthermore, it is necessary to carry out a connection to a high-speed tester having high function used in the scanning path methodology, thereby performing measurement according to the control of the tester. In a test to be carried out in the BIST circuit, an expensive tester is often caused to stand by as a simple waiting time processing. Therefore, a test cost is not reduced. In order to eliminate such a drawback, the present inventors previously proposed a technique referred to as a so-called “logic with test function” in which a logic tester is constructed in a chip to carry out a self test, wherein a test circuit other than the BIST is provided in a chip to carry out measurement. In this methodology, an expensive tester is not required. Therefore, the test cost can be reduced considerably. In the same manner as in the BIST methodology, however, there has been a problem in that the over-head of hardware is great and the yield of a product is reduced due to faults of a test circuit itself which is mounted on a chip.
In order to solve such a problem, the present inventors had proposed a technique referred to as a so-called “non over-head test technique” in which an FPGA (Field Programmable Gate Array) is provided on a chip and an ALPG (Algorithmic Pattern Generator) is constructed by the FPGA to generate a test pattern in accordance with a predetermined algorithm to carry out a test and to reconstruct an ordinary logic circuit on the FPGA after the test ends (International Publication WO00/62339). According to this technique, a circuit referred to as a so-called self-testability type FPGA capable of detecting a self fault is provided in a user logic circuit and a test circuit is constituted to carry out a self test and to finally mount a user circuit on the FPGA, thereby reducing the over-head of hardware with test circuit mounting. In this technique, the FPGA is set to be the self-testability type circuit. Therefore, fault exposure is detected by itself and information about a fault portion is output to the outside, and a circuit can be constituted except for the fault portion when constructing a logic tester on the FPGA through a test HDL (Hardware Description Language) or constituting a user circuit. Therefore, there has been a character that a reduction in yield can be avoided.
Then, the present inventors have further investigated the technique referred to as the so-called “non over-head test technique” described above. As a result, it has been apparent that there are the following drawbacks. For example, in this technique, it is necessary to introduce a novel device process referred to as the FPGA. Although semiconductor manufactures providing the FPGA or a product mounting the FPGA to the market can implement this technique by slightly changing a process, general semiconductor manufactures do not manufacture the FPGA or the product mounting the FPGA. In order to develop this technique, therefore, it is necessary to design the FPGA and to improve a novel process for forming the FPGA on a semiconductor chip.
Moreover, the present inventors have proposed a technique referred to as a so-called “self-configuration chip” for memory device redundancy separately from the above-mentioned design for testability. In this technique, a memory is utilized as a re-configuration logic circuit by writing truth data of a combination circuit to the memory, inputting an address and outputting a predetermined logic result. The output of the memory is fed back to the input so that a sequential circuit as well as the combination circuit can be constituted. Therefore, the present inventors found that a so-called “self-configuration chip” capable of constituting an optional logic can be implemented and therefore filed the application. The present inventors further invented that application of the “self-configuration chip” technique to the “non over-head test technique” do not require the FPGA and the problem of the design of the FPGA and the development of the process can be solved.
It is, therefore, an object of the present invention to provide, without introducing a novel device process referred to as the FPGA, a semiconductor integrated circuit device and a method of manufacturing the semiconductor integrated circuit device in which a test circuit is provided in a chip to test a logic circuit in the chip so as to be capable of performing a logic test having less overhead.
The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.
SUMMARY OF THE INVENTION
The summary of the typical invention disclosed in this application will be described below.
More specifically, the present invention provides a semiconductor integrated circuit device comprising a storage circuit capable of reading and writing data in response to an input of an address signal, and a feedback path for feeding back a signal corresponding to data read from the storage circuit to an input terminal side of the address signal, wherein an input signal of a logic circuit is input as the address signal to the storage circuit and data are written to the storage circuit such that the data read from the storage circuit are changed into a logical output signal expected to the input signal so that the storage circuit can be operated as a logic circuit having desirable logic function.
According to the above-mentioned means, the storage circuit provided in the semiconductor integrated circuit device can be utilized as the logic circuit. Therefore, the test circuit for checking the other circuit in a semiconductor chip can be constituted on the storage

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