Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-11-05
2003-06-10
Smith, Matthew (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C382S146000, C365S052000
Reexamination Certificate
active
06578175
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electrical computers and digital processing systems for instruction processing, and relates more particularly to specialized instruction processing in support of testing, debugging and emulation of integrated-circuit chip designs stored on a computer.
2. Description of the Related Art
Computer-aided design (CAD) programs are widely used in the field of integrated-circuit (I-C) chip design. Many CAD programs, such as the CADENCE suite of programs by CADENCE DESIGN SYSTEMS, INC., allow designers to input a multitude of design parameters for a propose d I-C chip in order to achieve a desired functionality. A typical process for the conception, design and manufacture of an I-C chip is described as follows.
As an initial step in the design process, a proposed functionality for an I-C chip is presented to and analyzed by one or more chip designers. The designers then determine the logical components that may be required to achieve the desired functionality. The designers next place the components in a virtual layout using a computer workstation, such as those commonly manufactured by SUN MICROSYSTEMS, in conjunction with logic design tools provided by a CAD program which may run thereon.
Designers generally employ hierarchical design techniques to determine the appropriate selection and interconnection of logic and/or electrical components which will enable the chip to perform with the desired functionality. These techniques involve describing the chip's functionality at various levels, ranging from the most general function performed by the chip to the precise functions performed by each logic or electrical component placed in the virtual layout. Each of the multiple levels of a proposed I-C chip design are typically specified in the virtual layout.
A final virtual I-C layout will describe multiple layers of a physical I-C chip wherein a substrate forms the base layer with varying amounts of polysilicon and or/or metal. Metal layers are then stacked with alternating layers of dielectric material between each layer. “Via” or “thrash” connections and contacts provide electrical communication between each layer. The levels described above may not always correspond one-to-one with each physical layer.
A common method for accomplishing the virtual I-C layout involves the use of a machine-readable hardware description language (HDL) which is employed by a CAD program. HDL languages often contain specific functions and syntax that allow complex hardware structures to be described in a compact and efficient way. Using an HDL also allows a designer to specify components of the I-C chip at any level. For example, the I-C chip may be defined as many individual small building blocks or cells. Alternatively, many or all such cells may be combined and stored as a single larger cell. Standard cells (for example, NAND gates, OR gates, flip-flops, multiplexors, and the like) are typically provided in a design library contained in the CAD program. Non-standard or user-defined cells may also be created, defined and stored by the designer in the design library.
Once the virtual I-C layout is completed, it is typically stored in a database format so that the logical and functional relationships of the components of the design can be simulated by the CAD program. One such database format is the DF II standard recognized by CAD programs such as CADENCE. If errors are detected during a simulation of the design, they are generally displayed to the designer on an output device, such as a monitor or printer. The errors are then fixed manually by the designer by rearranging, adding or deleting components of the I-C layout. The corrected I-C layout is then re-tested. These simulations are repeated in an iterative manner until the I-C layout produces satisfactory results, after which manufacturing of an I-C chip corresponding to the virtual layout can be commenced in any known manner.
Certain I-C chip designs typically contain varying amounts of polysilicon and metal. Regardless of any specific amounts used, it is well known in the art that a ratio of metal in a particular layer of a chip to the area of that layer should be within a certain tolerance of a target ratio which describes the total amount of metal on a chip to the entire area of the chip. The same applies for materials such as polysilicon. An appropriate target ratio for metal or polysilicon and the maximum deviation therefrom for a given I-C chip is usually application specific, rather than a fixed number. However, after the required ratios have been determined, if it is discovered that a ratio for any given layer of the chip falls outside that range, certain manufacturing problems may arise. These problems include localized hot spots, flaking, feature deformation, as well as other yield problems known to those of ordinary skill in the art. Thus, lack of uniform ratios are one type of error that must be checked for and corrected during the simulation of a virtual I-C chip layout.
CAD programs of the prior art provide a first error checking process which compares the ratio of metal or polysilicon for a given layer of a chip to that for a total area of the chip. Such programs further provide reports on those areas which violate a predetermined acceptable range of values. However, after such errors are displayed, the designer must revisit the chip design and correct the erroneous areas manually. To correct the errors for, say, an out-of-range metal ratio, the designer must insert metal fill in the affected area of chip when the ratio is below the required range, or delete metal fill from the affected area of the chip when the ratio exceeds the required range. After such insertion or deletion, the error-checking utility must be run again to determine whether the erroneous values have been properly corrected. This first error correction process must be repeated in an iterative manner until the ratio falls within the prescribed range, thus adding an inordinate amount of time and inefficiency to the I-C chip design process.
In addition, any metal fill inserted in a layer of the design as a result of the foregoing must be further re-checked in a violation checking process wherein it is determined whether short circuits, fill isolation violations, antenna violations and the like have resulted from such insertion. This second process must also be repeated in an iterative manner until any such unacceptable violations become negligible. This correction process, therefore, also adds an inordinate amount of time and inefficiency to the I-C chip design process.
As a result, there is a need for an automated apparatus and method for evaluating and correcting errors in integrated circuit chip designs which minimizes or eliminates the foregoing problems.
BRIEF SUMMARY OF THE INVENTION
In order to address and solve certain of the foregoing shortcomings in the prior art, the present invention provides a method and accompanying apparatus for evaluating and correcting a virtual integrated circuit design. The method comprises: (1) receiving a layout for an integrated circuit having a material covering a portion of an area thereof; (2) receiving a target ratio of the material to the area of the integrated circuit; (3) selecting a layer of the layout; (4) determining a material ratio of the material to an area of the selected layer; (5) comparing the material ratio to the target ratio; and (6) adjusting an amount of the material in the layer based on the comparing step.
The adjusting step may include adjusting a material based on an only deletion method, an only scaling method, a combined deletion and scaling method and a striping method. The method and apparatus of the present invention further allows for the automatic detection and correction of violations, such as fill isolation violations, antenna violations, short circuits, and the like which result from the adjusted material.
It is therefore an advantage of the present invention that error checking and correcting processes are
Benevit Carl A.
Dias Shane S.
Moucheron Matthew M.
Pantone John Anthony
Sharpe John Michael
Agere Systems Inc.
Do Thuan
Mendelsohn Steve
Smith Matthew
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