Active solid-state devices (e.g. – transistors – solid-state diode – Test or calibration structure
Reexamination Certificate
2001-05-01
2003-04-01
Abraham, Fetsum (Department: 2826)
Active solid-state devices (e.g., transistors, solid-state diode
Test or calibration structure
Reexamination Certificate
active
06541791
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method and system for semiconductor die testing, and particularly to a method and system for multi-channel testing wherein the channels are fewer than the total pins of the dies to be tested.
2. Description of the Prior Art
FIG. 1
is a block diagram of a conventional semiconductor die test system. The system comprises a handler
1
, a testing device
2
and an interface
3
.
The handler
1
comprises an accepter
13
which accepts a wafer (not shown). One of the dies
11
on the wafer is tested by the system. The die
11
has 8 pins p1~p8. A display
14
in the handler
1
displays testing results of the pins p1~p8 read by the handler
1
through channels
15
a
~
15
h.
The testing device
2
comprises a tester
22
and a test module
21
corresponding to the die
11
. When an embedded memory test is carried out, the tester
22
controls the test module
21
to generate a group of test signals to the pins p1~p8 of the die
11
through a bus L
1
. Then, the test module
21
derives a group of testing results through the bus L
1
and transfers them to the tester
22
. On the other hand, when logic testing is carried out, the test module
22
is bypassed and the tester
22
directly tests the die
11
.
The tester
22
transfers the received testing results to the interface
3
through a bus L
2
and then the testing results are input to the channels
15
a
~
15
h
through a bus L
3
.
FIG. 2
is a flow chart of a test method for the above test system.
First, in step
21
, a die on a wafer is selected. Logic testing of the selected die is carried out.
Next, in step
22
, an embedded memory test is carried out.
Finally, in step
23
, if there is another die on the wafer to be tested, steps
21
and
22
are repeated. Otherwise, the test is finished.
The test method for the conventional test system is sequential, i.e. the dies to be tested must be processed one by one if there are not enough channels. The duration of testing will be increased proportionally to the number of the dies to be tested. Thus makes the conventional test method time-consuming. Additionally, embedded memory testing is much more time-consuming than logic testing. 95% of the total duration of die testing is for embedded memory testing. A fast embedded memory test will effectively reduce the total testing duration.
Besides, in the conventional test system, the number of the pins of the die to be tested should match that of the channels. For example, a handler with 16 channels matches a die with 8 pins because two of the dies can be tested at one time by the handler without any channel left unused. On the other hand, the handler does not match a die with 9 pins because only one of the die can be tested at one time and 7 of the channels are left unused.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a method and system for semiconductor die testing with a shorter testing duration.
To achieve the above-mentioned object, the present invention provides a multi-channel semiconductor test system for testing a plurality of pins of at least a die, the system comprising a testing device, a handler and a multiplexer. The testing device tests the pins of the die and derives a plurality of testing results. The handler has a plurality of channels fewer than the pins and the testing results are read by the handler through the channels. The multiplexer receives and sequentially outputs the testing results, whereby the testing device derives all the testing results simultaneously and sequentially outputs the testing results to the handler through the channels.
The present invention further provides a multi-channel semiconductor test system for testing a plurality of dies, the system comprising: a testing device, a handler and a multiplexer. The testing device tests the dies and derives a plurality of groups of testing results. The handler has a group of channels and the groups of testing results are read in group by the handler through the group of channels. The multiplexer receives and sequentially outputs the groups of the testing results, whereby the testing device derives all the groups of the testing results simultaneously and sequentially outputs the groups of the testing results in group to the handler through the group of the channels.
The present invention further provides a test method for a plurality of semiconductor dies, wherein a plurality of test modules in corporation with a handler having a group of channels tests the dies and derives a plurality of groups of testing results, and the handler reads the groups of the testing results in group through the group of the channel. The method comprises the steps of controlling the test modules, simultaneously generating corresponding test signals to the dies, deriving the groups of the testing results, and sequentially outputting the groups of the testing results in group to the handler through the group of channels.
In the present invention, a multiplexer is provided to sequentially output the testing results to the handler. This allows embedded memory testing to be carried out simultaneously for all the dies to be tested, even if the channels are fewer than the pins of the dies.
REFERENCES:
patent: 4989209 (1991-01-01), Littlebury et al.
Abraham Fetsum
Ladas & Parry
Winbond Electronics Corp.
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