Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-03-12
2003-09-30
Fahmy, Wael (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S308000, C438S396000
Reexamination Certificate
active
06627941
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a capacitor for a semiconductor device and, more particularly, to a capacitor for a Dynamic Random Access Memory (DRAM) type semiconductor memory device that is able to effectively increase its capacitance and simplify its manufacturing process.
2. Related Art
There are generally two kinds of capacitor types for a semiconductor device: a stacked capacitor type and a trench capacitor type. The stacked capacitor type is divided into, e.g., a fin type structure, a cylindrical type structure, a box type structure, and other type structures.
A stacked capacitor type having a cylindrical type structure has a storage node electrode forming a cylindrical structure. In order to obtain sufficient cell capacitance, the cylindrical structure has been known to be most suitable for a semiconductor memory device having a 64 Mb or higher memory capacity.
Depending on the number of cylindrical structures and their types, a capacitor of a cylindrical type structure is divided into, e.g., a 1.0 cylinder-type capacitor, a 1.5 cylinder-type capacitor, a 2.0 cylinder-type capacitor, and a higher number cylinder-type capacitor.
Such cylinder-type capacitors have the following disadvantages.
First, a 1.0 cylinder-type capacitor has only one cylinder, which places restrictions on having an increased surface area. This is disadvantageous in providing accumulative capacitance for a cylinder-type capacitor. Second, in the case of a 2.0 cylinder-type capacitor, two cylinders are used, requiring more processing steps. This reduces high production yield and complicates the overall manufacturing process. Third, in the case of a 1.5 cylinder-type capacitor, it is difficult to control a profile of the cylinder-type capacitor using an etching process.
A conventional method for manufacturing a capacitor for a semiconductor device will be described with reference to the accompanying drawings.
Referring to
FIGS. 1
a
through
1
d,
a conventional method for manufacturing a capacitor for a semiconductor device is illustrated.
First, an insulating material, e.g., an oxide layer, is deposited on a silicon substrate
10
having impurity diffusion regions (not shown) formed therein and cell transistors (not shown) formed thereon, thereby forming a first insulating layer
11
, as shown in
FIG. 1
a.
Next, a silicon nitride layer
12
is formed on the first insulating layer
11
, and subsequently a photoresist layer (P/R) is deposited and patterned on the silicon nitride layer
12
. With the patterned photoresist layer (P/R), which serves as a mask, the silicon nitride layer
12
and the first insulating layer
11
thereunder are selectively removed to form storage node contact holes
13
.
As illustrated in
FIG. 1
b,
a first polysilicon layer, which forms first storage node electrodes
14
, is formed in the storage node contact holes
13
and on portions of the silicon nitride layer
12
. An oxide layer is deposited on the first polysilicon layer by a chemical vapor deposition (CVD) method, so as to form a second insulating layer
15
. Then, a photoresist (P/R′) layer is deposited and patterned on the second insulating layer
15
. With the photoresist pattern serving as a mask, the second insulating layer
15
and the first polysilicon layer are selectively removed, thereby forming the first storage node electrodes
14
.
Subsequently, as shown in
FIG. 1
c,
a second polysilicon layer, which forms second storage node electrodes
16
, is formed on the remaining second insulating layer
15
and on portions of the silicon nitride layer
12
. Then, the second polysilicon layer is subjected to etch back to form the second storage node electrodes
16
on the sides of the second insulating layer
15
.
Referring to
FIG. 1
d,
the second insulating layer
15
, which is surrounded by the first and second storage node electrodes
14
and
16
, is removed using a wet-etching process, thereby forming the first and second storage node electrodes
14
and
16
of a capacitor. Even though not shown in the figures, in the following step, a dielectric layer and an upper electrode are deposited on the upper portions of the first and second storage node electrodes
14
and
16
, thereby completing the capacitor (having a 1.0 cylindrical type structure).
Referring to
FIGS. 2
a
through
2
f,
another conventional method for manufacturing a capacitor of a semiconductor device is illustrated.
First, as shown in
FIG. 2
a,
an insulating material, e.g. an oxide layer, is deposited on a silicon substrate
17
having impurity diffusion regions (not shown) formed therein and cell transistors (not shown) formed thereon, thereby forming a first insulating layer
18
. Next, a photoresist layer (not shown) is deposited and patterned on the first insulating layer
18
.
Then, using the patterned photoresist layer as a mask, the first insulating layer
18
is selectively removed to form a storage node contact hole
24
. Thereafter, a first polysilicon layer
19
is formed on the entire surface of the first insulating layer
18
to a thickness that fills the storage node contact hole
24
. An oxide layer is deposited on the first polysilicon layer
19
by using a CVD method, so as to form a second insulating layer
20
.
Subsequently, a photoresist layer (P/R) is deposited and patterned on the entire surface of the second insulating layer
20
. With the patterned photoresist layer, which serves as a mask, the second insulating layer
20
is selectively removed.
Referring to
FIG. 2
b,
a second polysilicon layer
21
is formed on the entire surface of the first polysilicon layer
19
inclusive of the second insulating layer
20
.
Referring to
FIG. 2
c,
a third insulating layer
22
is formed on the second polysilicon layer
21
.
Referring to
FIG. 2
d,
insulating sidewalls
23
are formed on the sides of the second polysilicon layer
21
by subjecting the third insulating layer
22
to etch back. Thus, portions of the third insulating layer
22
become the insulating sidewalls
23
.
Referring to
FIG. 2
e,
using the second insulating layer
20
and the insulating sidewalls
23
as masks, the first and second polysilicon layers
19
and
21
are selectively etched. At this time, since the first polysilicon layer
19
is thicker than the second polysilicon layer
21
, as shown in
FIGS. 2
b
and
2
c,
during the etching process the second polysilicon layer
21
on the second insulating layer
20
is etched to expose the second insulating layer
20
. Also, the first polysilicon layer
19
not corresponding to the second insulating layer
20
and insulating sidewalls
23
is selectively removed to have a predetermined thickness.
Finally, as seen in
FIG. 2
f,
the remaining second insulating layer
20
and the insulating sidewalls
23
are completely removed, thus forming a storage node electrode of a capacitor (having a 1.5 cylinder-type structure with a protruding part in a center portion).
Even though not shown in the figures, in the following processing step, a dielectric layer and an upper electrode are deposited on the storage node electrode, thereby completing the capacitor.
In a conventional method for manufacturing a capacitor for a semiconductor device, capacitance is increased by increasing the height of the cylinder pillar of a cylindrical structure, which increases the surface area of the lower electrode. This is accomplished by increasing the height of an oxide layer and the height of a polysilicon layer. But this method is limited because of disadvantages in planarization.
Further, variation in the forms of cylinders may be one method for increasing capacitance. However, this method is difficult in obtaining the process tolerance for keeping up with the higher integration trend. This results in a low efficiency.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a capacitor for a semiconductor device that effectively increases capacitance and simplifies its manufacturing process for substantially obviating one or more
Hynix / Semiconductor Inc.
Peralta Ginette
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