Electronic digital logic circuitry – Multifunctional or programmable – Having details of setting or programming of interconnections...
Reexamination Certificate
2001-11-06
2003-06-03
Tokar, Michael (Department: 2816)
Electronic digital logic circuitry
Multifunctional or programmable
Having details of setting or programming of interconnections...
C326S040000, C326S041000, C365S236000, C365S189020
Reexamination Certificate
active
06573748
ABSTRACT:
FIELD OF THE INVENTION
This invention relates generally to programmable logic devices, and in particular to programmable logic devices that select from among a plurality of memory spaces during partial or complete reconfiguration.
BACKGROUND
A programmable logic device (PLD) is a well-known type of digital integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. PLDs are becoming ever more popular, largely because they are less expensive in relatively small quantities and require less time to implement than semi-custom and custom integrated circuits.
FIG. 1
(prior art) is a block diagram of one type of PLD, a field-programmable gate array (FPGA)
100
. FPGA
100
includes an array of configurable logic blocks (CLBs)
110
that are programmably interconnected to each other and to programmable input/output blocks (IOBs)
120
. The interconnections are provided by a complex interconnect matrix represented as horizontal and vertical interconnect lines
130
and
140
. This collection of configurable elements and interconnect may be customized by loading “configuration data” into internal configuration memory cells (not shown) that define how the CLBs, interconnect lines, and IOBs are configured. The configuration data may be read from memory. (e.g., an external PROM) or written into FPGA
100
from an external device. The collective program states of the individual memory cells then determine the function of FPGA
100
.
FIG. 2
depicts a typical programmable-logic system
200
in which a memory
205
stores the requisite configuration data for defining the logical function of an FPGA
210
. Memory
205
is, in one example, a member of the Spartan ® family of PROMs available from Xilinx, Inc., of San Jose, Calif. It is important to note, however, that myriad forms of memory are suitable for storing configuration data. In a recent example, configuration data has been conveyed to remote sites via the Internet.
Prior to configuration, FPGA
210
resets an address counter in memory
205
by providing a logic zero to a reset and output-enable pin OE/RESET bar on memory
205
. Then, during configuration, terminal CCLK from FPGA
210
drives a data clock CLK on memory
205
as configuration data transfers from an output terminal DATA to an input terminal DIN of FPGA
210
. FPGA
210
asserts (drives high) a DONE signal at the close of configuration. The high DONE signal de-asserts the chip-enable terminal CE bar of memory
205
. The process of loading configuration data is repeated each time FPGA
210
is powered on or reset.
It is sometimes desirable to provide a programmable logic device with a number of potential configuration options. Assuming, for example, that an FPGA is to be used as a signal processor, it might be useful to provide different configurations for the FPGA so the chip could easily be adapted for use with more than one communication standard.
System
200
offers a limited ability to provide alternative configurations. Multiple configurations can be stored in successive series of memory locations within memory
205
. Upon power-up, the internal address counters in memory.
205
are reset so configuration begins with the first program stored in memory. Holding the output-enable pin low leaves the address counters unchanged after configuration is complete. Pulling the DONE line low then begins a new configuration, this time from where the address counters left off after the first configuration. FPGA
210
is then reconfigured with the second program in memory. For a more detailed discussion of system
200
, see the Xilinx product specification entitled “Spartan Family of One-Time Programmable Configuration PROMs (XC17S00), ” DS030 (v1.7), Apr. 7, 2001, which is incorporated herein by reference.
System
200
is problematic for a number of reasons. First, the method fails if a user applies a reset during the configuration process because the address counter will not properly reset. This method must therefore never by used where there is any chance of a reset during configuration. Moreover, it can be difficult to update the contents of PROM
205
in the field, so system
200
offers limited flexibility.
FIG. 3
(prior art) depicts a system
300
that addresses some of the deficiencies of system
200
of FIG.
2
. System
300
includes an FPGA
305
adapted to receive configuration data from either a PROM
310
or a RAM
315
. System
300
employs parallel memories because they are available in greater storage capacities than serial memories, but either type can be used.
System
300
also includes a second programmable logic device, CPLD
320
, which acts as an interface to load configuration data from one of the memories to FPGA
305
. In the parallel mode, CPLD
320
generates the memory-addresses and includes the requisite logic to differentiate between memories
310
and
315
, depending upon the storage location of the desired configuration data. FPGA
305
identifies the memory from which to extract configuration data by providing an appropriate logic level on an I/O pin configured to provide a memory-select signal MS to a like-named input of CPLD
320
. The I/O pins of° FPGA
305
are tri-stated during reconfiguration, so CPLD
320
latches the memory select signal before reconfiguring FPGA
305
. Line MS connects a programmable I/O pin of FPGA
305
to a programmable I/O pin of CPLD
320
. A pull-down resistor ensures that the initial configuration is selected from PROM
310
. Alternatively, CPLD
320
can provide a pull-down signal for this purpose. Serial data systems similar to system
300
typically use a CPLD to increment addresses and select between memories. For a more detailed discussion of system
200
, see the Xilinx Advance Application Note entitled “Configuring Spartan-II FPGAs from Parallel EPROMs,” XAPP178 (v0.9) Dec. 3, 1999, which is incorporated herein by reference.
System
300
provides the desired functionality, but at the added expense and complexity of an additional integrated circuit. There is therefore a need for a simpler and less expensive system, for configuring a, programmable logic device from one of a number of sets of configuration data.
SUMMARY
The present invention is directed to programmable logic systems in which programmable logic devices can select from among a plurality of memory spaces from which to receive configuration data. In some embodiments, an input/output block of a programmable logic device is adapted to store a value identifying a remote memory space as a source of reconfiguration data. In other embodiments, external memory spaces for storing configuration data are adapted to store the value. In either case, the programmable logic device can be configured to control the source of data from which the device will be reconfigured.
The claims, and not this summary, define the scope of the invention.
REFERENCES:
patent: 5923614 (1999-07-01), Erickson et al.
patent: 5999020 (1999-12-01), Volk et al.
patent: 6031391 (2000-02-01), Couts-Martin et al.
patent: 6191608 (2001-02-01), Cliff et al.
patent: 6239613 (2001-05-01), Reddy et al.
patent: 6326806 (2001-12-01), Fallside et al.
Xilinx, Application Note, XAPP178 (v0.9), “Configuring Spartan-II FPGAs from Parallel EPROMs”, published Dec. 3, 1999, pp. 1-9, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Xilinx Product Specification DS030 (v1.7) “Spartan Family of One-Time Programmable Configuration PROMs (XC17S00)” Apr. 7, 2001, pp. 1-9, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Xilinx Product Specification DS026 (v2.9) “XC18V00 Series of In-System Programmable Configuration PROMs” Sep. 28, 2001, pp. 1-18, available from Xilinx, Inc., 2100 Logic Drive, San Jose, California 95124.
Behiel Arthur J.
Tan Vibol
Tokar Michael
Xilinx , Inc.
Young Edel M.
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