Computer graphics processing and selective visual display system – Computer graphics display memory system – Frame buffer
Reexamination Certificate
2000-09-25
2003-06-03
Saras, Steven (Department: 2675)
Computer graphics processing and selective visual display system
Computer graphics display memory system
Frame buffer
C345S098000, C365S189120
Reexamination Certificate
active
06573901
ABSTRACT:
TECHNICAL FIELD
The present invention pertains generally to interface circuitry for video display devices and pertains more specifically to an improved half-frame buffer for use in a video display device controller.
BACKGROUND ART
Digital display devices such as liquid crystal display (LCD) panels, thin-film-transistor (TFT) panels and plasma panels are used in various applications such as personal computer systems, a variety of hand-held devices such as a so called Personal Digital Assistant (PDA), and micro-processor based industrial controllers to present visual images. Digital display devices are being incorporated into additional types of applications as manufacturing costs of the display devices continue to decrease.
Some display devices use multiple display components or panels such as LCD panels to present a single image. An implementation using multiple LCD panels, for example, is attractive because it allows a display device to be made with smaller, lower cost LCD panels. In principle, any number of display components may be used; however, a typical implementation uses two. In a typical two-panel implementation, one display panel is used to present the upper half of the image and the other display panel is used to present the lower half of the image.
Electronic circuitry sometimes referred to as a video adapter or a display controller provides an interface between a digital display device and various other components that provide the digital information representing an image to be presented. In typical applications, a display controller receives digital information that represents the image to be presented and, in response, generates frames of output digital signals arranged that convey a representation of the image comprising individual picture elements or “pixels” arranged in rows. Each “frame” of the output signals causes an attached digital display device to present a complete rasterized image. The output digital signals are generated by the display controller to meet the input signal requirements of the display device.
When a display device incorporates two display panels to present a single image, the display controller can use what is know as a half-frame buffer to improve the quality of the presentation by reducing image flicker. This is accomplished by concurrently providing half-frame output signals for each display panel. The display controller uses the half-frame buffer to store a previously generated half-frame output signal for one display panel while the half-frame output signal is being generated for the other display panel. A typical method for using a half-frame buffer is described in the following paragraph.
As the display controller receives image information to be presented by the first display panel, it passes this image information immediately to the display device. Concurrently, the display controller also fetches from the half-frame buffer image information to be presented by the second display panel and passes this information to the display device. The display controller then stores the image information for the first display panel in the half-frame buffer. Subsequently, the display controller receives image information to be presented by the second display panel and passes this image information immediately to the display device. Concurrently, the display controller fetches from the half-frame buffer the image information to be presented again by the first display panel. The display controller then stores the image information for the second display panel in the half-frame buffer.
A display controller usually has a bus or set of parallel circuit paths for handling digital image signals in a parallel form. The width of these buses or parallel paths has been increased to satisfy the demand for high-performance presentation of images with higher spatial resolution and finer gradations of color or shading. Widths of 32 bits are commonly used and greater widths of 64 bits or more will become more common as higher levels of display performance are required.
Typically, a half-frame buffer comprises serial and parallel storage registers that are implemented by flip-flops. Unfortunately, the number of flip-flops required to implement these registers is proportional to width of the parallel circuit paths mentioned above and has grown as this width has been increased. The growing number of flip-flops required to implement these registers is undesirable because more circuit board space is required for the hardware components that implement the registers. This prevents or restricts the degree to which a display controller can be made smaller as other advances in circuit miniaturization are realized. In addition, more power is required to operate the increasing number of flip-flops, which increases heat generation and reduces battery life in portable applications.
DISCLOSURE OF INVENTION
It is an object of the present invention to provide for a half-frame buffer in a display controller that has lower implementation and operation costs.
According to one aspect of the present invention, a display controller that provides output signals representing pixels in a color image for presentation on a display device comprises a first storage register to receive first parallel signals conveying bits representing all of the colors in a plurality of colors; a second storage register coupled to the first storage register to receive second parallel signals representing a first set of bits representing all of the colors in the plurality of colors; an information-storage memory; a memory-access controller coupled to the information-storage memory to retrieve second information from a location in the information-storage memory that represents a second set of bits representing all of the colors in the plurality of colors and to provide fourth parallel signals conveying the second information, and coupled to the second storage register to receive third parallel signals conveying first information that represents the first set of bits and to write the first information to the location in the information-storage memory; and an output-interface circuit coupled to the memory-access controller to receive signals conveying the second information and, in response, to generate output signals representing the second information as a portion of the image for presentation by the display device.
According to another aspect of the present invention, a buffer in a display controller that provides output signals representing pixels in a color image for presentation on a liquid crystal display panel comprises an LCD interface circuit having inputs coupled to video memory; a distribution circuit having inputs coupled to outputs of the LCD interface circuit; a first storage register having parallel inputs coupled to outputs of the distribution circuit; a second storage register having parallel inputs coupled to parallel outputs of the first storage register; information-storage memory; and a memory-access controller having parallel input/output ports coupled to the information-storage memory, having parallel inputs coupled to parallel outputs of the second storage register, and having outputs coupled to inputs of the LCD interface circuit.
According to yet another aspect of the present invention, a method for receiving and storing information in a buffer of a display controller that provides output signals representing pixels in a color image for presentation on a display device comprises steps that perform the acts of receiving a plurality of digital signals, each signal conveying a sequence of bits representing a respective color in a plurality of colors for each of the pixels; distributing a first set of bits conveyed by the digital signals into information-storage cells of a first storage register such that the first storage register stores information representing all of the colors in the plurality of colors; sending parallel signals representing the first set of bits as stored in the first storage register to information-storage cells in a second storage register; retrieving second i
Alphonse Fritz
Saras Steven
Seiko Epson Corporation
Watson Mark P.
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