Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
2000-11-15
2003-04-15
Siek, Vuthe (Department: 2825)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000, C716S030000, C716S030000
Reexamination Certificate
active
06550048
ABSTRACT:
TECHNICAL FIELD OF THE INVENTION
This invention relates generally to the field of system design and more specifically to a method and system for determining repeater allocation regions.
BACKGROUND OF THE INVENTION
Determining repeater placement is critical in designing circuits. Inserting repeaters in a path of an interconnect improves a signal traveling on the path. There are, however, regions of the circuit where a repeater cannot be located, for example, a region designated for another element. Moreover, certain arrangements of repeaters fail to satisfy constraints applied to the circuit or fail to optimize performance of the circuit. Accordingly, determining repeater placement has posed challenges for circuit designers.
SUMMARY OF THE INVENTION
In accordance with the present invention, a method and system for determining repeater allocation regions are provided that substantially eliminate or reduce the disadvantages and problems associated with previously developed systems and methods.
According to one embodiment of the present invention, a method for determining a repeater allocation region is disclosed. A path delay equation describing a path delay from a driver to a gate is formulated. A delay constraint is applied to the path delay equation. A repeater allocation region indicating a position of a repeater is determined from the path delay equation.
According to another embodiment of the present invention, a system for determining a repeater allocation region is disclosed. A path delay module formulates a path delay equation describing a path delay from a driver to a gate. A processor applies a delay constraint to the path delay equation, and determines a repeater allocation region from the path delay equation. The repeater allocation region indicates a position of a repeater.
According to yet another embodiment of the present invention, logic for determining a repeater allocation region is disclosed. The logic formulates a path delay equation describing a path delay from a driver to a gate. The logic also applies a delay constraint to the path delay equation, and determines a repeater allocation region from the path delay equation. The repeater allocation region indicates a position of a repeater.
Embodiments of the invention may provide numerous technical advantages. A technical advantage of one embodiment is that repeater allocation regions are determined that allow circuit designers to optimally place repeaters on a circuit. Repeater allocation regions represent regions where a repeater may be placed while satisfying a delay constraint, and may be determined in one, two, or three spatial dimensions. Circuit designers may use the repeater allocation regions to determine an arrangement of repeaters without wasting circuit area.
Another technical advantage of one embodiment is that an optimal number of repeaters may be determined. Given a delay constraint, an optimal number of repeaters that satisfies the delay constraint may be calculated. Alternatively, an optimal number of repeaters may be calculated for a net, without given a delay constraint. Accordingly, embodiments provide for determination of an optimal number and placement of repeaters on a circuit.
Another technical advantage of one embodiment is that the embodiment may be used to determine repeater allocation regions for system design, interconnect design, circuit design, board design, and backplane design, among other areas of computer design.
REFERENCES:
patent: 5557779 (1996-09-01), Minami
patent: 6412101 (2002-06-01), Chang et al.
Baker & Botts L.L.P.
Levin Naum
Silicon Graphics Inc.
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