Memory cell having reduced leakage current

Static information storage and retrieval – Systems using particular element – Flip-flop

Reexamination Certificate

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Details

C365S156000

Reexamination Certificate

active

06549451

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to memory cells. More particularly, the invention relates to memory cells having improved retention time.
BACKGROUND OF THE INVENTION
Integrated circuits (ICs) such as digital signal processor s (DSPs) include on-chip memory to store information. The on-chip memory typically comprises, for example, an array of static random access memory (SRAM) cells connected by word lines in one direction and bit lines in another direction. The information stored in the SRAM cells are maintained until power is removed from the IC. Sense amplifiers are coupled to the bit lines to facilitate memory accesses, such as reads or writes. A sense amplifier is coupled to a pair of bit lines and senses a differential voltage indicative of the information stored in the selected memory cell on the bit line pair.
FIG. 1
shows a conventional SRAM cell
101
. The SRAM cell comprises first and second transistors
110
and
120
coupled to a latch
130
, which stores a bit of information. One transistor is coupled to a bit line
140
and the other is coupled to a bit line complement
141
while the gates are coupled to a word line
135
. The latch includes first and second inverters
133
and
134
, each implemented with two transistors. As such, the SRAM cell is realized using six transistors.
Smaller SRAM cells using less than six transistors have been proposed to reduce chip size. However, the charge stored in such cells dissipates overtime due to current leakage. To prevent the charge from dissipating below an undefined logic level (logic 0 or 1), the memory cell must be refreshed. Typically, refreshing of memory cells interrupts the normal operation, thus adversely impacting the performance of the IC.
As evidenced from the above discussion, it is desirable to provide a memory cell with improved charge retention time to decrease refresh frequency.
SUMMARY OF THE INVENTION
The present invention relates generally to memory cells. More particularly, the invention relates to reducing leakage current in memory cells. In one embodiment, the memory cell comprises a plurality of first access transistors coupled to a first terminal of a storage transistor and a second access transistor coupled to a second terminal of the storage transistor. Bit lines are coupled to the access transistors and word lines are coupled to the gates of access transistors. In one embodiment, the word lines comprise a negative voltage in the inactive state. The negative voltage reduces leakage current from the memory cell.


REFERENCES:
patent: 4805148 (1989-02-01), Diehl-Nagle et al.
patent: 5774393 (1998-06-01), Kuriyama

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