Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-04-25
2003-12-16
Coleman, William David (Department: 2823)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C257SE21547, C257SE21556
Reexamination Certificate
active
06664182
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates a method for improving the interlayer adhesion property of low-k layers in a dual damascene process, and more particularly, to improve the interlayer adhesion property of low-k layers in a dual damascene process which do not require a silicon nitride layer or a silicon oxide layer to act as a stop layer. It can improve the interlayer adhesion property between the low-k layers in a dual damascene process to avoid the peeling phenomenon in the low-k layers and the oxidation layer.
2. Description of the Prior Art
The dual damascene process is a method of stacking structures for forming a metal wire and a plug simultaneously. The method is used to connect the different elements and wires between each layer in a semiconductor wafer, while inter-layer dielectrics are used as isolators from other elements. Since copper metal (Cu) in recent years has been developed with a low resistance, the method of a copper metal dual damascene interconnect in the multi-layer interconnect process has become very important.
Please refer to
FIG. 1
of a schematic diagram of a dual damascene structure
11
according to the prior art. As shown in
FIG. 1
, a semiconductor wafer
10
comprises a bottom copper wire
14
inlayed in a first low-k layer
12
and an upper copper wire
24
inlayed in a trench structure
23
of a second low-k layer
20
. The upper copper wire
24
and the bottom copper wire
14
connect with a barrier layer
18
between the first low-k layer
12
and the second low-k layer
20
through a via
22
. Wherein the low-k materials are spin-coated both on the first low-k layer
12
and the second low-k layer
20
, and the low-k materials have parameters consistent with those of FLARE™ to reduce the RC delay effect between the wires.
The prior art process has to form an oxidation layer
21
to be a dual damascene etch stop layer in the second low-k layer
20
. However, the low-k materials has a problem of difficult adhesion to the oxidation layer
21
, leading to the second low-k layer being peeled off in the subsequent process.
SUMMARY OF THE INVENTION
It is therefore a primary objective of the present invention to provide a method for a dual damascene interconnect process that does not require a silicon nitride layer or a silicon oxide layer to be a stop layer.
The present invention also provides a method for improving the dual damascene interconnect process. The method not only improves the interlayer adhesion property between the low-k layers in a dual damascene process, but also avoids the peeling phenomenon between the low-k layer and the oxidation layer.
These and other objective of the present invention will no doubt become obvious to those of ordinary skill in the art after having read the following detailed description of the preferred embodiment which is illustrated in the various figures and drawings.
REFERENCES:
patent: 6225204 (2001-05-01), Wu et al.
patent: 6316351 (2001-11-01), Chen et al.
Coleman William David
Hsu Winston
Macronix International Co. Ltd.
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