Metal working – Method of mechanical manufacture – Electrical device making
Reexamination Certificate
2001-06-25
2003-12-30
Arbes, Carl J. (Department: 3729)
Metal working
Method of mechanical manufacture
Electrical device making
C029S841000, C029S832000, C174S255000, C174S260000
Reexamination Certificate
active
06668449
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to ball grid array packages. More specifically, this invention relates to a method of using a single solder resist opening on a ball grid array substrate as both a saw fiducial and a pin one indicator.
2. State of the Art
Integrated circuits (ICs) are typically fabricated on a semiconductor wafer. To achieve the many semiconductor devices which may be formed thereon, the semiconductive wafer is subjected to deposition, etching, planarization and lithographic processes. The wafer is then cut or “diced” to form multiple semiconductor die (dice) or semiconductor devices (IC chips). Typically, these individual semiconductor devices are transferred to a mounting substrate by an automatic “pick and place” process. Thereafter, a semiconductor device is electrically connected to the substrate and encapsulated by a molding apparatus into a final package. As trends continue towards higher performance, high input/output, and high board-manufacturing-yield, Ball Grid Array (BGA) packaging has become the technology of choice. In an ever increasing number of semiconductor applications, therefore, semiconductor devices or IC chips are mounted onto printed circuit boards or other mounting substrates which utilize BGA packaging methods.
Currently, some types of BGA packages, including fine pitch ball grid array (FPBGA) and micro ball grid array (&mgr;BGA) semiconductor device packages, are known in the art. The various types of BGA packages that have been developed include BGAs mounted on printed wiring boards, leadframes, and flexible tape. Presently, due to the need for smaller devices having a higher lead count and a smaller footprint, BGAs are used in chip scale packaging with increasing frequency.
One type of BGA package, known as “board-on-chip,” is shown in drawing
FIGS. 1 and 2
. A board-on-chip BGA package
1
typically comprises a substrate
10
having an upper or top surface
12
, an opposing bottom surface
16
, and an elongated aperture
15
extending through the middle thereof Substrate
10
is typically a polymer laminate printed circuit board, although ceramics and other types of substrates may be used. During a die attach process, a semiconductor die
20
is mounted on the bottom surface
16
of the substrate
10
using an adhesive, adhesive and tape and/or adhesively coated tape, having active surface
22
of semiconductor device
20
upwardly facing and positioned below aperture
15
. Active surface
22
of semiconductor device
20
is configured having a plurality of bond pads
24
in single or multiple columns thereon which are substantially aligned with aperture
15
as illustrated therein. As illustrated in drawing
FIG. 1
, bond pads
24
can be viewed through aperture
15
as they are substantially aligned. Upper surface
12
of substrate
10
comprises a conductor surface wherein circuit traces
17
are formed, typically by etching, in a desired pattern. Alternatively, circuit traces
17
are formed on the semiconductor device side of substrate
10
, or are formed internally within substrate
10
. Circuit traces
17
are interconnected with a plurality of bond pads
18
and an array of contact pads
19
located along the periphery of aperture
15
and extending from circuit traces
17
, respectively. Bond pads
18
and contact pads
19
are generally located at separate terminal ends of circuit traces
17
, as can be seen in drawing FIG.
1
. Contact pads
19
are formed in arrays of varying numbers, dependent upon the specific application of the package. Each contact pad
19
typically comprises a solderable surface mount pad which is formed of a conductive metal, such as copper.
As shown in drawing
FIG. 2
, substrate
10
also includes a laminated or screen printed solder resist layer, or solder mask
40
. Solder mask
40
is formed over top and bottom surfaces
12
and
16
and comprises an electrically insulating, low surface tension material which shields conductive members on top and bottom surfaces
12
and
16
, respectively, from subsequent soldering and/or plating operations that might result in electrical shorts. The layer of solder resist comprising solder mask
40
initially may, if desired, cover all portions of surfaces
12
and
16
(including bond pads
18
and contact pads
19
), with the exception of a semiconductor device receiving area of the substrate
10
.
In a subsequent step, a pattern of via openings
42
is created in solder mask
40
, via openings
42
corresponding to portions of bond pads
18
and contact pads
19
to which conductive elements, such as conductive wires
26
and solder balls
30
, are respectively attached. To mask the areas over bond pads
18
and contact pads
19
, solder mask
40
must obviously be deposited in a thickness at least minimally greater than the height of bond pads
18
and contact pads
19
. Typically, the solder mask used to cover substrate
10
is a photoimageable material that can be blanket deposited as a wet or dry film. By using photolithographic processes, vias or openings
42
of predetermined diameters are formed by exposing and developing a desired pattern on the resist areas through a photoimaging mask, resulting in the removal of resist material and the exposure of bond pads
18
and contact pads
19
.
Through a wire bonding process, conductive wires
26
extend from bond pads
24
of semiconductor device
20
through aperture
15
to bond pads
18
located in the wirebonding area on terminal end portions of circuit traces
17
on or within substrate
10
. Conductive wires
26
serve to electrically connect the bond pads
24
of semiconductor device
20
to contact pads
18
of substrate
10
. In turn, bond pads
18
are electrically connected to contact pads
19
by circuit traces
17
. Contact pads
19
are then placed in contact with respective electrically conductive, connective elements such as solder balls
30
. Alternatively, solder balls
30
are placed directly upon, or in electrical communication with, the termination point of a selected circuit trace
17
. Solder balls
30
may be filled with any suitable metal, such as gold, although other conductive metal-based solder balls or conductive filled epoxy materials are frequently used. As illustrated in drawing
FIG. 2
, conductive wires
26
, die bond pads
24
, and bond pads
18
are shown covered with a layer of protective encapsulant
25
. An encapsulant layer
25
is also shown covering the inactive backside surface of semiconductor device
20
and bottom surface
16
of substrate
10
.
Bond pad geometries are typically formed as a standard round shape. Because of the excellent self-centering property of solder ball interconnections, BGA applications have significantly greater misalignment tolerances than other interconnection techniques, such as quad flatpack leads. As such, relatively wide variations in solder ball placement are accommodated during reflow of the solder joints. Generally, the rule of thumb is that solder balls must have a radial placement accuracy wherein the solder is at least “half on pad.”
Generally, the types of bond pad layouts presently known in the art are Solder Mask Defined bond pad layouts and Non-Solder Mask Defined bond pad layouts. In Solder Mask Defined layouts of bond pads, the opening in the solder resist defining the solder ball mounting area is made smaller than the copper, or any suitable type metal, bond pad disposed underneath. Thus, the solder mask overlaps with the edge of the copper pad. This arrangement carries with it the advantage of providing better copper pad definition, since Solder Mask Defined layouts of bond pads are located by photoimaging, rather than by copper etching as is the case for Non-Solder Mask Defined pads.
In contrast, bond pads which are formed by Non-Solder Mask Defined layouts of bond pads have a solder mask opening which is larger than the copper pad, or any suitable type metal pad. In this situation, the size of the copper defines the size of the pad, and the size of the pad
Rumsey Brad D.
Schwab Matt E.
Arbes Carl J.
Trinh Minh
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