Semiconductor static random access memory device

Details Semiconductor static random access memory device Semiconductor static random access memory device

2001-07-17

2003-07-22

Munson, Gene M. (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S903000

Reexamination Certificate

active

06597041

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to an SRAM (Static Random Access Memory) provided with memory cells, each of which includes six MOS (Metal Oxide Silicon) transistors, and will be referred to as a “full CMOS cell” hereinafter, as well as a method of manufacturing the same. More particularly, the invention relates to a structure of a memory cell of an SRAM, which can reduce an area of the memory cell.
2. Description of the Background Art
In accordance with lowering of voltages used in SRAMs, SRAMs provided with memory cells of a high resistance load type or a TFT load type, each of which has four MOS transistors and two loads, were in the mainstream when the lowered voltage was 3 volts or higher.
In recent years, however, the voltage has been further lowered to 2.5 V, 1.8 V or 1.5 V. In accordance with this, the SRAMs of the high resistance load type or TFT load type, which were in the mainstream, have declined due to inferior operation characteristics, and the SRAMs provided with the full CMOS cells each having six MOS transistors are becoming mainstream.
The full CMOS cell is generally a memory cell formed of two bulk access nMOS transistors, two bulk driver nMOS transistors and two bulk load pMOS transistors.
An example of a layout of a conventional full CMOS cell is described in Japanese Patent Laying-Open No. 10-178110. The layout described in this publication is shown in FIG.
26
.
As shown in
FIG. 26
, a full CMOS cell in the prior art has p- and n-wells arranged alternatively in the lateral direction. On the p-wells, nMOS transistors
50
a
-
50
d
are formed. Also, pMOS transistors
51
a
and
51
b
are formed on the n-well. Further, polycrystalline silicon layers
52
-
55
, which form gates of these transistors, are formed.
As shown in
FIG. 26
, many contact holes
56
a
-
56
i
and via holes
57
a
-
57
i
are formed for connecting the gates and impurity regions of the respective MOS transistors to the upper level interconnections.
In the example shown in
FIG. 26
, contact holes
56
b
and
56
f
are arranged above inverter gates, and contact holes
56
e
and
56
g
independent of contact holes
56
b
and
56
f
are arranged between the inverter gates. Therefore, it is necessary to ensure spaces D
1
and D
2
between contact hole
56
e
and the inverter gates, and it is also necessary to ensure spaces D
3
and D
4
between contact hole
56
g
and inverter gates. Therefore, large spaces are required between the inverter gates, resulting in increase in memory cell area.
SUMMARY OF THE INVENTION
The invention has been developed for overcoming the above problems, and an object of the invention to reduce an area of a full CMOS cell.
A semiconductor memory device according to the invention includes memory cells each including first and second access MOS transistors, first and second driver MOS transistors and first and second load MOS transistors, a first well region of a first conductivity type for forming the first driver MOS transistor and the first access MOS transistor thereon, a second well region of the first conductivity type for forming the second driver MOS transistor and the second access MOS transistor thereon, a third well region of a second conductivity type formed between the first and second well regions for forming the first and second load MOS transistors thereon, a first gate forming gates of the first driver MOS transistor and the first load MOS transistor, a second gate for forming gates of the second driver MOS transistor and the second load MOS transistor, a first contact hole formed in a self-aligned fashion with respect to the first and second gates, and reaching one of impurity regions of the first driver MOS transistor, one of impurity regions of the first load MOS transistor and the second gate, a first local interconnection formed in the first contact hole, and electrically connected to the first driver MOS transistor, the first load MOS transistor and the second gate, a second contact hole formed in a self-aligned fashion with respect to the first and second gates, and reaching one of impurity regions of the second driver MOS transistor, one of impurity regions of the second load MOS transistor and the first gate, and a second local interconnection formed in the second contact hole, and electrically connecting the second driver MOS transistor, the second load MOS transistor and the first gate.
As described above, each of the first and second contact holes extends from the first or second gate to the predetermined impurity region. Therefore, it is not necessary to employ a conventional structure shown in
FIG. 26
, in which independent contact holes
56
b
,
56
d
,
56
g
and
56
f
spaced from each other are formed in the positions on the first and second gates as well as in the positions between the first and second gates. Therefore, spaces D
1
and D
4
in
FIG. 26
can be reduced, and the space between the first and second gates can be smaller than that in the prior art. Further, spaces D
2
and D
3
in
FIG. 26
can be reduced because the first and second contact holes are formed in the self-aligned fashion with respect to the first and second gates. This also contributes to reduction in space between the first and second gates.
Preferably, the first and second contact holes have the same form. Thereby, the form and size of the local interconnections can be uniform so that transfer and etching for forming the local interconnections can be performed easily.
Preferably, the semiconductor memory device according to the invention includes a first interlayer insulating layer covering the first and second gates, a second interlayer insulating layer formed on the first interlayer insulating layer, a first metal interconnection formed on the second interlayer insulating layer, and extending in a direction of alignment of the first, second and third well regions for forming a word line, and a plurality of second metal interconnections formed on the first metal interconnection with a third interlayer insulating layer therebetween for forming a bit line (BIT line), a ground line (GND line) and a power supply line V
DD
line. Thereby, the first and second metal interconnections can be formed to satisfy characteristics required therein. Since the memory cell is long in the extending direction of the word line, the space between the second metal interconnections can be increased by arranging the second metal interconnections in this extending direction. Thereby, the second metal interconnection can be formed easily.
Preferably, the semiconductor memory device according to the invention includes a plurality of third contact holes for electrically connecting the second metal interconnections to the predetermined MOS transistors, the first and second contact holes are formed in the first interlayer insulating layer, and the third contact holes extend through the first and second interlayer insulating layers, and are formed in a self-aligned fashion with respect to the first or second gate.
Thereby, the first and second contact holes can be formed in a step different from that of forming the third contact holes, which are different in form from the first and second contact holes, so that the first, second and third contact holes can be formed easily. The space between the third contact hole and each of the first and second contact holes can be smaller than that in the case of simultaneously forming these contact holes.
Preferably, the first metal interconnection has a smaller thickness than the second metal interconnection.
The space between the first metal interconnections is narrow in many cases. Therefore, the smaller thickness of the first metal interconnection allows easy formation of the first metal interconnection. This improves the yield of manufacturing.
The first and second metal interconnections may be made of different materials, respectively. The material of the first metal interconnection may have a higher resistivity than the material of the second metal interconnection. More specifically, t

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