Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2001-11-19
2003-06-17
Zarabian, Amir (Department: 2822)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S582000, C438S618000, C438S643000, C438S652000, C438S682000, C438S685000
Reexamination Certificate
active
06579786
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention in general relates to a technique for depositing a two-layer diffusion barrier on a semiconductor wafer. In particular, the invention relates to a technique for depositing a diffusion barrier consisting of a tantalum nitride (TaN) layer and an overlying tantalum (Ta) layer as the carrier layer for interconnects, which are in particular copper interconnects of wiring planes.
Interconnects typically consist of wiring planes of microelectronic modules made of aluminum; however, this is limited with respect to the electrical conductivity and the realizable structural widths. For this reason, a new technology was developed for purposes of utilizing copper for the interconnects, the core idea of which is the dual damascene design, also known as the ticking design (D. Edestein, J. Heidenreich, R. Goldblatt, W. Cote, C. Uzoh, N. Lustig, P. Poper, T. McDevitt, W. Motsiff, A. Simoon, L. Su, S. Luce, J. Slattery, IEEE VLSI Tech. Symp. 1997). In this technique, the negative form of the junction hole and interconnect is etched in a planar silicon oxide layer of the intermetallic dielectric in a first step. A barrier and a copper start layer are deposited in this negative form by sputtering. The copper start layer can be deposited electrochemically or by Cu-PVD (Physical Vapor Deposition) or CVD (Chemical Vapour Deposition). Next, the entire negative form is electrochemically filled with copper at a low temperature. Because a completely planar surface is needed on the semiconductor wafer for the subsequent layer structure, the excess copper is then removed by chemical mechanical polishing (CMP), so that the junction holes and interconnects remain in the silicon oxide.
Because copper is utilized for the interconnects instead of aluminum, the copper must be completely encapsulated by corresponding barriers in order to prevent it from diffusing into the silicon or into the intermetallic silicon oxide.
At present, primarily single-layer systems consisting of titanium nitride, tantalum and tantalum nitride are known as diffusion barriers to silicon oxide (P. Ding, T. Chiang, R. Tao, B. Sun, I. Hashim, T. Yao, L. Chen, G. Yao, B. Chin, R. Mosley, Z. Xu, F. Chen; Conference Proceedings VMIC Conference, Jun. 10-12, 1997).
Attempts have also been made to utilize a two-layer system as a barrier, for instance a titanium nitride/tantalum system, in order to minimize the layer resistance of the overall barrier layer and thereby minimize the junction hole resistance and optimize the barrier stability by exploiting cumulatively advantageous morphological characteristics of the barrier structure, as described in Published European Patent Application EP 0 751 566 A2. In the event that a two-layer TaN/Ta system is utilized, besides the greater barrier stability due to a thin TaN layer under the tantalum layer, it is already possible to produce the low-impedance a-phase of the tantalum at temperatures around 200° C. Otherwise, this type of tantalum layer can be realized only at unacceptably high deposition temperatures above 400° C. Another advantage of this two-layer barrier is that an optimal bond can be achieved with respect to both the silicon oxide and the copper.
Such two-layer systems are usually deposited in a PVD chamber at strictly prescribed temperatures. The temperature utilized for this is above 200° C., whereby the disadvantage of a deposition at such a high temperature is that the silicon wafer on which the barrier was deposited must then be cooled to a temperature below 50° C. The reason for this is that a copper start layer must be deposited at low temperatures, so that a conformal holeless copper film forms, and the copper does not agglomerate. The required cooling of the silicon wafer costs a great deal of time, which either limits the throughput of the sputter apparatus or raises the costs of the apparatus by an additional cooling chamber.
At present, in the process management which is provided for depositing a diffusion barrier deposit or seed deposit, the semiconductor wafer is pretreated in a degasifying or tempering step at >100° C. and then with argon at 250° C.-300° C. in a precleaning step. Immediately after that, the TaN layer and then the Ta layer are sputtered at approximately 250° C. Since the deposition of Cu must be conducted at low temperatures, the semiconductor wafer is cooled to 50°-25° in a subsequent processing step. This cooling process can also occur in a separate cooling chamber. Next, a copper start layer can be deposited at 25° C.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for depositing the two-layer diffusion barrier on a semiconductor wafer which overcomes the above-mentioned disadvantages of the prior art methods of this general type. In particular, it is an object of the invention to provide a method for depositing a two-layer diffusion barrier on a semiconductor wafer, wherein it is possible to achieve substantial time savings without additional apparatus costs, while the quality of the layer deposition remains the same.
The inventive object is achieved with a method of the above described type by depositing the two-layer diffusion barrier in a two-step process wherein the TaN layer is deposited given a high wafer temperature in the first step, and then the Ta layer is deposited given a low temperature near room temperature.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for depositing a two-layer diffusion barrier on a semiconductor wafer, that includes steps of: providing a two-layer diffusion barrier on a semiconductor wafer; providing the diffusion barrier with a bottom TaN layer and an overlying Ta layer serving as a carrier layer for interconnects; and depositing the TaN layer in a high-temperature deposition step with a semiconductor wafer temperature above 200° C., and subsequently depositing the Ta layer in a low-temperature deposition step with the semiconductor wafer temperature below 50° C.
The semiconductor wafer may be treated first in a degasifying or tempering step prior to the deposition of the two-layer diffusion barrier in order to eliminate adsorbents. Then in a subsequent precleaning step, the metal oxide layer, which is situated in the floor of the junction holes, of a bottom metal track that sits uncovered there may be removed by a physical sputter effect.
In accordance with an added feature of the invention, the high-temperature deposition of the TaN layer is preferably performed at above 200° C., and the low-temperature deposition of the Ta layer is performed at below 50° C., for instance at 25° C.
In accordance with an additional feature of the invention, in order to be able to perform the two-layer deposition within an optimal time, the deposition of the Ta layer is performed during the cooling of the semiconductor wafer to a temperature below 50° C.
In accordance with another feature of the invention, the deposition of the TaN layer and the Ta layer is performed in a PVD deposition apparatus, whereby the deposition of the TaN layer is performed in a nitrogen atmosphere.
In accordance with a further feature of the invention, the deposition of the TaN layer and the deposition of the Ta layer are performed in the same PVD chamber. Following the degasifying and precleaning steps, when the wafer has a temperature of 200 to 300° C., the semiconductor wafer is placed in the PVD chamber on an Electro Static Chuck (ESC) that has been tempered to 25° C. without being chucked, and the TaN layer is deposited in the nitrogen atmosphere, with the excess nitrogen being pumped out following the successful deposition of the TaN layer. Next, the semiconductor wafer is chucked on the ESC, and the Ta layer is deposited in a nitrogen-poor atmosphere during the cooling to the low temperature.
Instead of the two-layer deposition of the diffusion barrier in one PVD chamber, it is also possible to deposit the TaN layer and the Ta layer in separate PVD chambers. To accomplish this, fol
Ruf Alexander
Schmidbauer Sven
Soward Ida M.
Zarabian Amir
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