Plastic and nonmetallic article shaping or treating: processes – Mechanical shaping or molding to form or reform shaped article – To produce composite – plural part or multilayered article
Reexamination Certificate
2000-12-05
2003-05-13
Davis, Robert (Department: 1722)
Plastic and nonmetallic article shaping or treating: processes
Mechanical shaping or molding to form or reform shaped article
To produce composite, plural part or multilayered article
C264S272170, C425S123000, C425S444000, C425S556000
Reexamination Certificate
active
06562272
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to semiconductor chip manufacturing. More particularly, the embodiments of the present invention pertain to an apparatus and method for the delamination-resistant array type molding of increased mold cap size laminate packages.
BACKGROUND OF THE INVENTION
The manufacture of semiconductor chips is performed in multiple ways depending on the chip type. For instance, one mode of chip manufacture is an array type manufacture wherein multiple chips are simultaneously fabricated in arrays. Within this process a rectangular array of chips, such as a 5×5 array, is formed where the chips are formed or placed side by side in multiple rows. Each such rectangular array is commonly referred to as a block, and multiple blocks are formed and connected in a row to form a strip. The chips are soldered to a substrate sheet which is often a laminate of electrically conductive and non-conductive materials. The result may be referred to as a chip/substrate assembly.
On a single substrate sheet, multiple strips may be formed and connected to one another. The total number of chips manufactured on a substrate sheet in a single cycle of the manufacturing process is then equal to the number of chips in a block (25 for a 5×5 array) times the number of blocks per strip and times the number of strips per substrate sheet. Increasing the total chip count in a single cycle of manufacturing can therefore be gained by increasing the chip count per block, block count per strip, and/or strip count per sheet. The resulting increase in chip count per substrate sheet enhances the cost effectiveness of the manufacturing process.
One of the final steps in chip manufacture is packaging where the application of a protective coating over the chip/substrate assembly results in a chip laminate package. Following the build up of the chips themselves and the soldering of these chips to the substrate or laminate sheet, a ceramic or plastic layer is added over the chip/substrate assembly to prevent exposure of the chip circuitry to mechanical or chemical damage. The most typical chemical damage occurs from moisture entering the laminate package and corroding the circuitry.
The array type manufacture of multiple chips is used on BGA (Ball Grid Array) type chips. BGA chips have an array of solder balls placed on one side of the chip which provide for input/output to the chip assembly. The chips are placed onto the substrate such that the solder balls are in contact with appropriate contact points on the substrate and then the chips are soldered into place. Once soldered onto the substrate, the array of chips, grouped into blocks and with the blocks connected in strips, are then coated with a protective plastic covering. For BGA chip/substrate assemblies the molding process is a single sided molding process, that is the protective layer need only be molded on the side of the assembly to which the chips are soldered.
An approach known in the art for single sided molding onto a chip array is a molding process where the chip/substrate assembly is placed over a mold die where the mold die is contoured to create multiple cavities for forming a mold cap over each of the multiple blocks of chips soldered to the substrate. The mold die and chip/substrate assembly are held together while molten plastic is forced under pressure into the mold die cavities. Once the molten plastic has been allowed to cool, the mold die is removed from the surface of the resulting laminate package by pressing multiple pins against the substrate such that the chip/substrate assembly with newly molded protective layer is pushed from the mold die.
A key measure of chip manufacture and of plastic BGA package quality is the Moisture Sensitivity Level (MSL). The MSL scale ranges from 1 through 5, where a chip having an MSL rating of 1 is essentially insensitive to environmental moisture conditions while a chip having a MSL rating of 5 is very sensitive to environmental moisture and must be accordingly protected from exposure to moist environments. Chip packages commonly rate an MSL value of 3 and therefore have reduced life and reliability when exposed to moist environments.
Following the manufacturing process the chip laminate packages are commonly inspected for delamination of the molded protective layer from the chip substrate. The greater the delamination, the greater the likelihood for the ingress of moisture into the chip assembly, and resultingly, a more moisture sensitive laminate package results.
The conventional art in the packaging of array type chip laminate packages is described below in reference to
FIGS. 1 and 2
. A rectangular block of chips, commonly comprised in the industry of a n×m array, is arranged and soldered to a substrate sheet. Additionally, multiple blocks are arranged in a row on the substrate sheet to form a strip. The conventional art, shown in
FIG. 1
, is a cross section of the industry typical strip assembly combined with the mold die used for forming a mold cap over the chip/substrate assembly. Within the cross section, five chips
30
are shown arranged in a row across the width of the substrate sheet
10
and are soldered to the substrate sheet
10
prior to the molding process.
In the molding process common to industry, mold die
40
is clamped against substrate sheet
10
and molten plastic is forced into the mold die cavity to form mold cap
20
. Following the cool down and solidification of the molten plastic, the mold die
40
is separated from the newly formed laminate package
5
, shown in FIG.
2
and described below. The separation of the mold die
40
from the substrate sheet
10
of
FIG. 1
is achieved by forcing ejector pins
50
against the substrate
10
. The mold cap
20
is pulled from the mold die
40
by means of its adhesion to the substrate sheet
10
and chips
30
.
FIG. 2
shows a cross section view of the chip laminate package
5
achieved commonly in industry and corresponding to the mold die
40
of FIG.
1
. The industry typical chip laminate package
5
, shown in cross section in
FIG. 2
, contains chips
30
in rows five abreast which are soldered to substrate sheet
10
and covered by mold cap
20
.
Increased productivity in array type chip manufacture could be gained through increasing the number of chips manufactured in each array. One of the most efficient approaches would be to increase the chip count within each block. For example, increasing the chip array size within a block from 5×5 to 7×7 would result in a chip count increase of 96%.
However, attempts to gain manufacturing speed and efficiency by increasing the number of chips in each block beyond a 5×5 array have yielded unsatisfactory product. The result has been a greater percentage of poor quality chips in the array generally resulting from the chip array having a greater degree of delamination of the protective layer from the chip/substrate assembly and a concomitant increase in moisture sensitivity.
Additionally there is a desire to reduce the moisture sensitivity of chip laminate packages so that they may be stored and subsequently utilized without regard to environmental moisture levels. Chip laminate packages commonly achieve a MSL rating of 3. Achieving a MSL rating of 1 for laminate packages would practically eliminate the need to wrap laminate packages with a moisture-barrier. An MSL rating of 1 may also provide chips in laminate packages with longer shelf lives.
An apparatus and method is needed that reduces delamination in array type molding of laminate packages, enables larger chip array block sizes to be employed, and reduces in general the moisture sensitivity of chip laminate packages employing array type molding.
SUMMARY OF THE INVENTION
Accordingly, the present invention provides an apparatus and method for delamination-resistant, array type molding of chip laminate packages such that larger chip array block sizes may be employed. The invention further reduces in general the moisture sensitivity of chip laminate packages employing
Chang Bo
Tan Annie
Verma Vani
Cypress Semiconductor Corporation
Davis Robert
Wagner , Murabito & Hao LLP
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