Static information storage and retrieval – Read/write circuit – Signals
Reexamination Certificate
2002-04-05
2003-09-02
Hoang, Huan (Department: 2818)
Static information storage and retrieval
Read/write circuit
Signals
C365S189050, C365S233100
Reexamination Certificate
active
06614700
ABSTRACT:
BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The invention relates to a circuit configuration with a memory array, a memory access controller assigned to the memory array, a control unit, and an input/output circuit. The memory access controller is connected to the input/output circuit via a data bus. The control unit is connected to the input/output circuit via a first control line and to the memory access controller via a second control line. The control unit outputs a control signal simultaneously to the input/output circuit and to the memory access controller
In memory technology, semiconductor memories are used which have a memory array with a multiplicity of memory cells. Each individual memory cell can be accessed by means of a memory access controller for writing or reading. The memory access controller is connected via a data bus to an input/output circuit via which data is output onto the data bus or read out from the data bus. In order to control the writing and reading operations, a control unit is provided which is connected to the memory access controller and the input/output circuit via a control line. Corresponding circuit arrangements are provided, in particular, in dynamic memories with random access (DRAM). Because the memory capacitances of the dynamic memories are increasing further, this has had the effect that, even though technology is becoming more miniaturized, the surface of a memory module is becoming larger. In addition, the operating frequencies are increasing so that the requirements made in terms of timing precision of control signals and of data signals are increasing. Furthermore, owing to lines which are becoming longer, the signal edges of global signals are becoming increasingly flat owing to technological properties.
In addition, owing to the size of the memory module, differing lengths of control lines occur between a central control unit and a memory array or between the central control unit and the input/output circuit because the memory arrays are arranged around the control unit and the input/output unit is arranged in an edge region of the memory module. The control signals of the central control unit must, however, both be supplied to the memory array in a clock-synchronous fashion and be output by the input/output circuit in a clock-synchronous fashion. However, because the control lines have differing lengths, synchronization problems may occur because the propagation times are different and there are different line capacitances on the control lines owing to the lines with different lengths. As a result, the signal edges of the control signals for the memory access controller and for the input/output circuit have different degrees of steepness.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a circuit configuration with a control unit which overcomes the above-mentioned disadvantages of the heretofore-known devices and methods of this general type and wherein synchronization problems between components that are actuated by the control unit are reduced.
With the foregoing and other objects in view there is provided, in accordance with the invention, a circuit configuration, comprising:
a memory array and a memory access controller connected to the memory array;
an input/output circuit connected to the memory access controller through a data bus;
a control unit connected to the input/output circuit via a first control line and to the memory access controller via a second control line, the control unit outputting a control signal simultaneously to the input/output circuit and to the memory access controller; and
a delay circuit connected in the second control line, the delay circuit delaying the control signal by a given delay time.
An advantage of the invention is that a delay circuit, which brings about a delay of the control signal is provided in a control line. Owing to the delay in a control line, the timing of a control signal is adapted to the timing of a control signal of a second control line. In this way, synchronization of the control signals of the two components is achieved independently of the length of the control lines of the components to be controlled.
A further advantage of the invention is that the delay circuit has a predetermined line capacitance. The overall capacitance of the delay circuit and of the control line connected to the delay circuit is preferably defined in such a way that the overall capacitance is equal to the capacitance of the second control line. In this way, the delay circuit equalizes the capacitances of the first and the second control lines. As a result, the signal edges of the control signals which are transmitted via the first and second control lines are made identical. Additional precise matching of the time arrival of the control signal is thus made possible.
In accordance with an added feature of the invention, the second control line and the data bus are constructed with a substantially identical length.
In accordance with an added feature of the invention, the delay circuit includes a copy circuit effecting a delay of the control signal, the copy circuit is substantially identical in design to signal paths of the input/output circuit at least in components through which the control signal and the data in the input/output circuit pass, and which effect a delay between a time at which the control signal arrives at the input/output unit and a time at which data is output by the input/output unit upon receiving a control signal.
In accordance with an added feature of the invention, the delay time is approximately the time which the input/output circuit takes, after receiving the control signal, to output data onto the data bus.
In accordance with another feature of the invention, the copy circuit comprises a plurality of components corresponding to components of the input/output circuit defining signal paths thereof.
In accordance with a further feature of the invention, the copy circuit is manufactured using a technology equalling a technology in which the input/output circuit is manufactured.
In accordance with an additional feature of the invention, the second control line and the data bus are identical in terms a technology used to produce the second control line and the data bus.
In other words, the various advantageous embodiments of the invention provide for the following: In one preferred embodiment, a copy line is provided which is connected to the delay circuit. The copy line is constructed in the same way as the data line, and the data is fed from the input/output circuit to the memory access controller. In this way, the control signal experiences the same delay and the same capacitance as the data. Precise synchronization of the arrival of the control signal at the memory access controller and the arrival of the data can thus be achieved.
In a further advantageous embodiment, the delay circuit is constructed using the same technology as the signal path over which a control signal in the input/output circuit runs and causes data to be output onto the data bus. At least the components which bring about a delay of the control signal in the input/output circuit and a delay of the outputting of the data in the input/output circuit onto the data bus are even identical. This ensures that the delay between the arrival of the control signal at the input/output circuit and the outputting of the data from the input/output circuit is equal to the delay which a control signal will maintain in the first control line. The use of the same technology ensures that the matching of the timing is maintained even when the technology has changed. In this way, the chronological effect of the delay circuit is ensured independently of the selected technology which is used in the manufacture of the memory module.
In accordance with a concomitant feature of the invention, the delay circuit is a flip-flop having an input connected through to an output. In this simple embodiment, the delay circuit is constructed in the form of a connected-through flip-flop. A conne
Dietrich Stefan
Kieser Sabine
Schrögmeier Peter
Weis Christian
Greenberg Laurence A.
Hoang Huan
Infineon - Technologies AG
Locher Ralph E.
Stemer Werner H.
LandOfFree
Circuit configuration with a memory array does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Circuit configuration with a memory array, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Circuit configuration with a memory array will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3092276