Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
2000-07-27
2003-08-12
Everhart, Caridad (Department: 2825)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S612000
Reexamination Certificate
active
06605522
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device having a bump electrode as an electrode for inputting and outputting signals to and from a semiconductor element and a method for manufacturing the same, and in particular to a semiconductor device which can suppress occurrence of cracks at an area below the bump electrode upon the bonding of an inner lead and can achieve an enhanced heat resistance cycle property after the inner lead bonding has been carried out and a method for manufacturing the same.
2. Description of the Related Art Conventionally bump electrodes have been employed as those electrodes for a TAB type and a COB (chip on board) type semiconductor device.
FIGS. 1
to
3
, each, are a cross-sectional view showing a major section of a semiconductor device having a conventional bump electrode. This structure is disclosed, for example, in Published Unexamined Japanese Patent Application H-1-164041, but involves drawbacks as will be set out below.
As shown in
FIG. 1
, a bump electrode
102
is provided on a semiconductor substrate
101
. A resin film
103
is covered over the surface of the semiconductor substrate
101
except at the bump electrode
102
. The surface of the resin film
103
is flush with that of the bump electrode
102
at an area
105
adjacent the bump electrode
102
. The resin film
103
serves as a film for protection against any external mechanical damage due to a dicing process, etc., and can prevent a lead shorting whereby direct lead-to-substrate contact occurs. However, the aforementioned semiconductor structure has the following drawbacks. To be specific, upon the bonding of the lead to the device shown in.
FIG. 2
, the lead
107
is pushed with a pressure P by a bonding tool
106
, causing the lead
107
to be pushed into the bump electrode
102
. At this time, the bump electrode
102
is deformed so that a crack occurs in the resin film
103
as indicated by reference numeral
108
. There is a fear that, upon the occurrence of such a crack in the resin film
103
, water and harmful impurities will intrude into the substrate (device body)
101
via the crack
108
. This adversely affects the device reliability.
FIG. 3
is a cross-sectional view, as taken along line III—III in FIG.
2
. As shown in
FIG. 3
, the lead
107
makes direct contact with the resin film
103
in the semiconductor device of FIG.
1
. In this state, upon the thermocompression bonding of the lead
107
to the device, heat is transmitted via the lead
107
to the resin film
103
to cause the resin film
103
to be affected by the heat at an area (heat-affected area) indicated by reference numeral
109
in FIG.
3
. The resin film
103
, being so heat-affected, gives a bad effect to the device reliability. In addition to the aforementioned drawbacks encountered upon the pushing of the lead onto the bump electrode and upon the thermocompression bonding, an eutectic alloy, i.e., an alloy of tin (Sn) plated to the surface of the lead
107
and gold (Au) contained in the bump electrode
102
, is not adequately formed due to the lead
107
contacting with the resin film
103
upon the pushing of the lead
107
into the bump electrode
102
. As a result, the lead
107
is liable to be separated off the bump electrode
102
.
SUMMARY OF THE INVENTION
It is accordingly the object of the present invention to provide a semiconductor device which can suppress occurrence of cracks at an area below a bump electrode upon the bonding of an inner lead and can achieve an enhanced heat resistance cycle property after the bonding of the inner lead and a method for manufacturing the same.
According to one aspect of the present invention there is provided a semiconductor device comprising a semiconductor substrate, at least one bump electrode provided over the semiconductor substrate to allow signals to be input and output to and from a semiconductor device, and a resin film covered on a surface of the semiconductor substrate except at a top area of the bump electrode, wherein the top area of the bump electrode is more projected than a top area of the resin film.
According to another aspect of the present invention there is provided a method for manufacturing a semiconductor device comprising the steps of forming at least one electrode pad over a semiconductor substrate, providing an opening to a surface portion of the electrode pad after forming a passivation film over a surface of the semiconductor substrate and that of the electrode pad, forming a metal film over the surface of the electrode pad at an area of the opening and over the passivation film near the opening, providing a bump electrode over the metal layer, forming an organic insulating film over the bump electrode and passivation film, and etching back the organic insulating film to allow a top area of the bump electrode to be more projected than a top area of the organic insulating film.
The present device and method can suppress occurrence of cracks at an area below a bump electrode upon the bonding of an inner lead and can achieve an enhanced heat resistance cycle property after the bonding of the inner lead.
Additional objects and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
REFERENCES:
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patent: 3714520 (1973-01-01), Engeler et al.
patent: 5444022 (1995-08-01), Gardner
patent: 5538920 (1996-07-01), Wakabayashi
patent: 6245594 (2001-06-01), Wu et al.
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patent: 3-231435 (1991-10-01), None
patent: 4-53138 (1992-02-01), None
patent: 4-237149 (1992-08-01), None
patent: 63-36548 (1998-02-01), None
Ezawa Hirokazu
Miyata Masahiro
Everhart Caridad
Finnegan Henderson Farabow Garrett & Dunner L.L.P.
Kabushiki Kaisha Toshiba
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