Static information storage and retrieval – Read/write circuit – Testing
Reexamination Certificate
2002-09-09
2003-09-09
Ho, Hoai (Department: 2818)
Static information storage and retrieval
Read/write circuit
Testing
C365S230030
Reexamination Certificate
active
06618306
ABSTRACT:
BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a circuit configuration having a matrix including memory cells and an addressing device, and a method for manufacturing the circuit.
In conventional digital information memories, also referred to as stores, the memory cells form a matrix including M rows and N columns. To select a memory cell for writing or reading, a row line associated with the row in question and a column line associated with the column in question are actuated. The selective actuation of the row lines, that is to say, the “addressing” of the matrix rows, is normally performed by a row address decoder having outputs individually connected to the row lines and inputs for receiving the bits of a digital row address. In a similar manner, a column address decoder performs the selective actuation of the column lines.
To select from X possibilities, a number of bits is required that is equal to ld(X), that is to say, equal to the base 2 logarithm (logarithm to the base 2) of X, or equal to the next highest integer if such an logarithm is not an integer logarithm. Normally, the numbers of rows and columns M and N in a memory matrix are, respectively, integer powers of the number 2 so that precisely Z=ld(M) bits are required for the row address and precisely S=ld(N) bits are required for the column address.
Following its manufacture, a memory circuit can contain faults in the memory matrix. To overcome such a problem, there exists a practice to test the memory matrix before the memory circuit is used further and to replace those rows and columns in which a fault has been found with a respective fault-free row or column before the memory circuit is used. To such an end, the circuit is equipped with “redundant” columns and rows, in addition to the “regular” M rows and N columns, during actual manufacture. A faulty regular row or column can be replaced with a fault-free redundant row or column using a laser. However, because it is also necessary to test the redundant rows/columns in advance to detect any faults, additional ways are required for addressing them. The address connection contacts provided for addressing the regular rows/columns are not adequate in such a case.
For additional bits that need to be applied for the purpose of addressing the redundant rows and columns, separate connection contacts need to be provided. Even if, as is usual, the number of redundant instances is no greater than the number of regular instances, two bits are required to make the 1-out-of-4 decision for the choice between the regular row lines and the redundant row lines and between the regular column lines and the redundant column lines.
If the row address and the column address are successively applied to a chip containing a memory matrix having M regular rows and N regular columns and the associated address decoding device, then the total number of address connection contacts on the chip need not be greater than Z=ld(M) or S=ld(N), depending on which number is the greater of the two. In such a case, the two additional bits for the 1-out-of-4 decision can naturally likewise be applied in succession, i.e., one together with the row address and the other together with the column address so that only one additional connection contact is required for selecting between “regular” and “redundant”, as is disclosed from U.S. Pat. No. 5,732,029 to Lee et al. However, there are memory circuits that provide one address space for simultaneously applying both the row address and the column address; in such a case, addressing requires a number of Z+S address connection contacts, and the two supplementary bits for the aforementioned 1-out-of-4 decision need to be applied simultaneously, which would actually require two additional connection contacts.
Connection contacts need to have a large enough contact area to be able to attach the outwardly routed connecting wires. In the case of integrated circuits, the space taken up by these contact areas (“pads”) is extremely large in comparison with the actual circuit components, and such a space requirement demands precious silicon area. In the present state of miniaturization of memory circuits, a pad on the integrated semiconductor chip takes up a space equivalent to the space required by approximately one thousand memory cells.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a digital memory circuit and a method for manufacturing the circuit that overcomes the hereinafore-mentioned disadvantages of the heretofore-known devices and methods of this general type and that minimizes the number of connection contacts required for simultaneous row and column addressing in a memory circuit provided with an addressing device and having a memory matrix containing not only regular rows and columns but also additional instances of rows and columns.
With the foregoing and other objects in view, there is provided, in accordance with the invention, a digital circuit configuration, including an information memory having cells forming a memory matrix (
50
) with M rows, N columns, P additional rows, and Q additional columns, where P<M, Q<N, P has K≦(Z−2) bits for addressing P elements, and Q has L≦(S−2) bits for addressing Q elements, an addressing device having an address decoding device having inputs, an input circuit having address connection contacts for receiving externally applied row and column address bits, a number of the address connection contacts being equal to a sum Z+S, where Z is a number of bits required for addressing M elements and S is a number of bits required for addressing N elements, a control bit connection contact for receiving an externally applied first control bit, and a changeover device receiving the first control bit and second and third control bits respectively applied to two dedicated contacts of the address connection contacts, a device for transferring at least some of the applied address bits to the inputs of the address decoding device, and the changeover device, only when the first control bit has a given first binary value, setting a first operating state in which the address decoding device uses bits of all of the address connection contacts for addressing M selected rows and N selected columns in the memory matrix, and otherwise, depending on a given combination of values of the second and third control bits, selectively setting one of a second operating state, a third operating state, and a fourth operating state in which the address decoding device, respectively, uses bits from contacts of ones of the address connection contacts not dedicated to the second and third control bits for addressing M selected rows and a remaining set of Q columns, a remaining set of P rows and N selected columns, and a remaining set of P rows and a remaining set of Q columns.
The invention, thus, relates to a circuit configuration having a memory matrix that contains M regular rows and N regular columns and also has P additional rows and Q additional columns, and having an addressing device whose address connection contacts are sufficient precisely for simultaneously addressing the regular rows and columns. To be able to address the additional rows and columns as well, the invention additionally provides only a single control bit connection contact and a changeover device that responds to control bits from the control bit connection contact and from dedicated instances of the address connection contacts to associate applied address bits either with addressing of the regular rows and columns or with addressing of the additional rows and columns. To make such a configuration possible, the numbers P and Q are chosen such that the addressing of P elements requires at least two bits fewer than the addressing of M elements, and such that the addressing of Q elements requires at least two bits fewer than the addressing N elements.
By virtue of the invention, to address all of the rows and columns in the memory matrix, just a single a
Böhm Thomas
Kandolf Helmut
Lammers Stefan
Manyoki Zoltan
Greenberg Laurence A.
Infineon - Technologies AG
Mayback Gregory L.
Stemer Werner H.
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