Computer-aided design and analysis of circuits and semiconductor – Nanotechnology related integrated circuit design
Reexamination Certificate
1999-09-22
2003-04-01
Niebling, John F. (Department: 2812)
Computer-aided design and analysis of circuits and semiconductor
Nanotechnology related integrated circuit design
C716S030000
Reexamination Certificate
active
06543039
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates generally to a method of designing an integrated circuit and an apparatus for designing an integrated circuit, and more particularly to a hierarchical parallel processing method of LSI design layout data and an array restructuring method thereof, a CAD (Computer Assisted Design) tool for executing the same methods, and a recording medium recorded with a computer program for executing the same methods.
A layout of a large scale integrated (LSI) circuit has been hierarchically designed over the recent years, and therefore a method and an apparatus for processing design layout data at a high speed have involved the use of a method of processing the design layout data as its hierarchical structure is retained as it is, and a CAD tool. In this case, each of design cells structuring the hierarchical structure is treated in an as-is form of being the design cell.
On one hand, the CAD tool for processing in parallel the design layout data by use of a computer incorporating a plurality of tightly-coupled CPUs or a plurality of computers connected to a network, is used as a technology separate from the hierarchical data processing method.
All of these contrivances aim at speeding up the design layout data processing and reducing an operation-oriented storage file.
On the other hand, for speeding up the processing of the design layout data having a hierarchical structure and reducing the operation-oriented storage file, it is an importance point how an array cell expressed by repetitive pattern data is efficiently treated. The array cell normally involves the use of a secondary array with a large number of repetitions for a general-purpose memory product, and is also used for a memory device such as a RAM and a ROM of a microcomputer. In the case of hierarchically treating the LSI design layout data, when pattern data, cell data or other array data are so laid out as to be overlapped with an array cell data region, it is a data processing method which has hitherto been carried out that the array cell data is developed or converted into unit layout cell data and thus processed.
FIG. 18
is an explanatory diagram showing one example of a layout of an LSI having a hierarchical structure.
FIG. 19
is a block diagram showing the hierarchical structure of the LSI shown in FIG.
18
.
In the layout of he LSI shown in
FIG. 18
, as illustrated in the block diagram in
FIG. 19
, two pieces of cells A, one single cell B and six pieces of cells E are laid out on a Cell ROOT constituting one chip. Further, three pieces of cells C and two pieces of cells D are hierarchically laid out on the cell B. Herein, it is assumed that a size of the Cell ROOT be on the order of 10000 &mgr;m×10000 &mgr;m, a size of the cell A be on the order of 2000 &mgr;m×8000 &mgr;m, a size of the cell B be on the order of 3000 &mgr;m×3000 &mgr;m, a size of the cell C be on the order of 700 &mgr;m×700 &mgr;m, a size of the cell D be on the order of 1800&mgr;m×600 &mgr;m, and a size of the cell E be on the order of 500&mgr;m×1000 &mgr;m.
When treating the data while retaining the hierarchical structure of the LSI design layout, the cell has hitherto been dealt with in the as-is form of being the design cell irrespective of a magnitude (a magnitude of a data size) of the number of patterns contained in the design cell, or regardless of a magnitude of the size thereof. For instance, in the example shown in
FIG. 18
, there are considerable differences in terms of their sizes between the cell ROOT, the cell A, the cell B, the cell C, the cell D and the cell E, and hence these cells ROOT, A, B, C, D and E are treated in their as-designed forms regardless of a considerable difference in the number of patterns contained in the respective cells, i.e., in the data size therebetween. Therefore, when processing the design layout data in parallel by use of a computer incorporating a plurality of tightly-coupled CPUs or by use of a plurality of computers connected to a network, for example, the cell A and the cell E, which are considerably different in size, are treated as processed units at the same level. In an extreme case, a design cell containing only several pieces of pattern data, and an enormous design cell containing several millions of pieces of pattern data are treated as the processed units at the same level.
As a result, there arises the following big problem in the conventional parallel processing of the design layout data.
First, there are treated extremely various types of design cells and, in an extreme case, over several thousands of types of design cells, which leads to an increase in an overhead time for pre-processing/post-processing for starting up a job for executing the parallel processing.
Second, a data quantity of each design cell to be processed in parallel is not uniform and hence each parallel processing time is not uniform. The processing time for the enormous design cells is dominant as an element for determining a time length of the parallel processing time, with the result that an effect of the parallel processing is unable to exhibit.
Further, according to the prior art, when hierarchically treating the LSI design layout data, as in the case of the cells c and D disposed on the cell B, when the pattern data, the cell data or other array data are so disposed as to be overlapped with the array cell data region, the array cell data is developed or converted into unit layout cell data and thus processed. Therefore, it follows that a tremendous number of pieces of pattern data and unit layout cell data are to be treated. This might cause a problem in which the processing time elongates, and a problem in which a large capacity of operation-oriented storage file is needed.
SUMMARY OF THE INVENTION
It is a primary object of the present invention to provide an integrated circuit design apparatus and an integrated circuit design method which are capable of enhancing an efficiency of parallel processing of LSI design layout data while retaining a hierarchical structure by use of a computer capable of processing data in parallel.
According to a first aspect of the present invention, there is provided a method of designing an integrated circuit, comprising:
a step of making an internal cell composed of divided cells obtained by dividing a design cell specified by design cell data among pieces of integrated circuit design layout data on the basis of a cell division judging criterion, and of non-divided design cells other than the divided cells; and
a step of creating a plurality of unit groups of which data quantities are substantially equal to each other by combining the internal cells, and executing hierarchical parallel processing of the data contained in the internal cell per unit group.
According to a second aspect of the present invention, there is provided a method of designing an integrated circuit, comprising:
a first step of sequentially reading design cell data about design cells among pieces of integrated circuit design layout data stored in storage section;
a second step of, with reference to the design cell data and a predetermined cell division judging criterion, dividing into divided cells the design cell among the design cells which exceeds the cell division judging criterion, converting the design cell data into internal cell data about an internal cell consisting of the divided cell and the design cell other than the divided cell, storing the internal cell data in an internal format file created in said storage section, and recording a variety of information for identifying the respective internal cells and a quantity of the data contained in each internal cell in an internal cell identification number table created in said storage section;
a third step of repeating said first step and said second step till said first and second steps are completed with respect to all pieces of design cell data;
a fourth step of creating a plurality of unit groups by combining the internal cells so that the quantity of the
Niebling John F.
Whitmore Stacy A
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