Semiconductor integrated circuit device

Details Semiconductor integrated circuit device Semiconductor integrated circuit device

2001-02-12

2003-08-26

Dinh, Son T. (Department: 2824)

Static information storage and retrieval

Floating gate

Particular connection

C365S185050, C365S200000

Reexamination Certificate

active

06611458

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a semiconductor integrated circuit device, particularly to a semiconductor integrated circuit device preferable for carrying out defect redundancy of a memory cell array without increasing fabrication cost in a highly-integrated semiconductor integrated circuit using multiple layer wirings.
BACKGROUND OF THE INVENTION
Conventionally, in defect redundancy in multiple layer wirings, as a system of programming a location where the defect is disposed, there has been used a method of cutting polysilicon by laser beam or a method of cutting wirings by laser beam. The method is as described in an example executed in DRAM of IEEE International Solid-State Circuits Conference, Digest of Technical Papers, p.p. 418-419.
When introducing defect redundancy to a semiconductor integrated circuit, in order to reduce cost, the following elements must be considered.
(1) Preventing fabrication steps from increasing.
(2) Reducing chip area.
(3) Reducing testing and redundancy steps.
In view of the above-described elements, the above-described defect redundancy system of the conventional technologies poses the following problem.
(1) According to the cutting method by laser beams, first, after finishing a semiconductor integrated circuit at a wafer stage, inspection is carried out by using a probe, thereafter, cutting is carried out by using a cutting apparatus by laser beam. In the case of such the cutting system, other than newly requiring the laser cutting apparatus, time is taken in a series of steps from inspection by probe to cutting by laser beam. Therefore, testing steps including a redundancy step are complicated, resulting in an increase in cost.
(2) In order to melt and cut polysilicon by laser beam, it is necessary to previously remove an insulating film on polysilicon. However, according to a semiconductor integrated circuit using multiple layer wirings, an insulating film on polysilicon is thickened and the thicker the insulating film the more difficult removal thereof. Particularly, when wiring is carried out by copper, an insulating film is constituted by a structure of alternately laminating silicon nitride films and silicon oxide films and it is extremely difficult to remove the insulating film on polysilicon in such a structure. Further, although the copper wirings per se can be cut by laser beam as in the conventional example, the melting point of copper is higher than that of aluminum and laser beam for cutting needs larger energy. A structure at a surrounding of a portion to be cut may be damaged by the large energy of laser beam.
It is a problem to be resolved by the invention to provide a defect redundancy circuit resolving the problem of the defect redundancy circuit in multiple layer wirings and preventing fabrication cost, chip area and testing cost from increasing even in an integrated circuit using a multiple layer wiring process or copper wirings.
SUMMARY OF THE INVENTION
In order to achieve a solution of the above-described problem, according to an aspect of the present invention, there is provided a semiconductor integrated circuit device comprising a memory cell array including memory cells, redundant memory cells for substituting for deficient memory cells when there are the deficient memory cells having defects in the memory cell array, a nonvolatile memory for storing redundant address information based on the deficient memory cells, and a redundant decoder for controlling to switch a connection between an output from the memory cell array and an output from the redundant memory cells by the redundant address information stored to the nonvolatile memory, wherein the nonvolatile memory includes a first conductive type of a first semiconductor area and a second conductive type of a second semiconductor area provided along a main face of a semiconductor substrate and a floating gate arranged to interpose an insulating film between the first and the second semiconductor areas and the floating gate and data can be erased or written by applying predetermined voltage to a source area and a drain area of the second conductive type arranged at the first semiconductor area and the second semiconductor area.
Further, redundant data is written to the nonvolatile memory in testing the semiconductor integrated circuit mounted therewith.


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